| /external/llvm/test/Transforms/InstSimplify/ |
| select.ll | 6 %and1 = and i32 %x, -2
7 %and1.x = select i1 %cmp, i32 %and1, i32 %x
8 ret i32 %and1.x
16 %and1 = and i32 %x, -2
17 %and1.x = select i1 %cmp, i32 %x, i32 %and1
18 ret i32 %and1.x
26 %and1 = and i32 %x, -2
27 %and1.x = select i1 %cmp, i32 %and1, i32 %
[all...] |
| /external/llvm/test/Transforms/InstCombine/ |
| assume2.ll | 19 %and1 = and i32 %a, 7
20 ret i32 %and1
35 %and1 = and i32 %a, 7
36 ret i32 %and1
50 %and1 = and i32 %a, 7
51 ret i32 %and1
66 %and1 = and i32 %a, 7
67 ret i32 %and1
81 %and1 = and i32 %a, 7
82 ret i32 %and1
[all...] |
| logical-select.ll | 103 %and1 = and <2 x i64> %bc1, %sia
107 %or = or <2 x i64> %and1, %and2
125 %and1 = and <2 x i64> %bc1, %sia
129 %or = or <2 x i64> %and2, %and1
147 %and1 = and <2 x i64> %bc1, %sia
151 %or = or <2 x i64> %and1, %and2
169 %and1 = and <2 x i64> %bc1, %sia
173 %or = or <2 x i64> %and2, %and1
191 %and1 = and <2 x i64> %sia, %bc1
195 %or = or <2 x i64> %and1, %and
[all...] |
| assume.ll | 61 %and1 = and i1 %a, %b
62 %and = and i1 %and1, %c
93 %and1 = and i32 %a, 3
103 ret i32 %and1
117 %and1 = and i32 %a, 3
118 ret i32 %and1
124 %and1 = and i32 %a, 3
139 ret i32 %and1
145 %and1 = and i32 %b, 3
159 ret i32 %and1
[all...] |
| bit-checks.ll | 275 %and1 = and i32 %argc2, %argc ; <i32> [#uses=1]
276 %tobool = icmp eq i32 %and1, %argc2 ; <i1> [#uses=1]
288 %and1 = and i32 %argc, %argc2 ; <i32> [#uses=1]
289 %tobool = icmp eq i32 %argc2, %and1 ; <i1> [#uses=1]
301 %and1 = and i32 %argc2, %argc ; <i32> [#uses=1]
302 %tobool = icmp eq i32 %argc2, %and1 ; <i1> [#uses=1]
317 %and1 = and i32 %argc, %bc ; <i32> [#uses=1]
318 %tobool = icmp eq i32 %and1, %bc ; <i1> [#uses=1]
333 %and1 = and i32 %bc, %argc ; <i32> [#uses=1]
334 %tobool = icmp eq i32 %and1, %bc ; <i1> [#uses=1
[all...] |
| /external/llvm/test/CodeGen/SystemZ/ |
| vec-or-02.ll | 14 %and1 = and <16 x i8> %val1, %val3
16 %ret = or <16 x i8> %and1, %and2
29 %and1 = and <16 x i8> %val1, %not
31 %ret = or <16 x i8> %and1, %and2
42 %and1 = and <8 x i16> %val1, %val3
44 %ret = or <8 x i16> %and1, %and2
55 %and1 = and <8 x i16> %val1, %not
57 %ret = or <8 x i16> %and1, %and2
67 %and1 = and <4 x i32> %val1, %val3
69 %ret = or <4 x i32> %and1, %and
[all...] |
| risbg-02.ll | 103 %and1 = and i32 %y, -65536
104 %or = or i32 %conv, %and1
115 %and1 = and i32 %y, -16777216
116 %or = or i32 %conv, %and1
|
| and-02.ll | 209 %and1 = and i64 %a, -4294967296
212 %or = or i64 %and1, %ext
221 %and1 = and i64 %a, -4294967296
224 %or = or i64 %and1, %ext
|
| vec-abs-01.ll | 120 %and1 = and <16 x i8> %shr, %neg
125 %ret = or <16 x i8> %and1, %and2
138 %and1 = and <16 x i8> %shr, %val
144 %ret = or <16 x i8> %and1, %and2
|
| /external/llvm/test/CodeGen/Hexagon/ |
| fusedandshift.ll | 12 %and1 = and i32 %shr1, 15
13 %conv2 = trunc i32 %and1 to i16
|
| /external/llvm/test/CodeGen/Mips/ |
| fcopysign.ll | 11 ; 32: and $[[AND1:[0-9]+]], ${{[0-9]+}}, $[[MSK1]]
15 ; 32: or $[[OR:[0-9]+]], $[[AND0]], $[[AND1]]
24 ; 64: and $[[AND1:[0-9]+]], ${{[0-9]+}}, $[[MSK1]]
27 ; 64: or $[[OR:[0-9]+]], $[[AND0]], $[[AND1]]
44 ; 32: and $[[AND1:[0-9]+]], ${{[0-9]+}}, $[[MSK1]]
48 ; 32: or $[[OR:[0-9]+]], $[[AND0]], $[[AND1]]
|
| cannot-copy-registers.ll | 13 %and1 = and i32 %0, 4
15 ([7 x i8], [7 x i8]* @.str, i32 0, i32 0), i32 %and1)
|
| micromips-andi.ll | 11 %and1 = and i32 %0, 4
13 ([7 x i8], [7 x i8]* @.str, i32 0, i32 0), i32 %and1)
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| partially-dead-super-register-immediate.ll | 19 %and1 = and i64 %lshr, 2190433320969 ; (255 << 33) | 9
20 %vec = bitcast i64 %and1 to <2 x i32>
|
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-bitfield-extract.ll | 83 %and1 = and i64 %shr, 16777215
84 %or = or i64 %and, %and1
99 %and1 = and i32 %shr, 7
100 %or = or i32 %and, %and1
118 %and1 = and i32 %shr, 7
119 %or = or i32 %and, %and1
139 %and1 = and i32 %shr, 7
140 %or = or i32 %and, %and1
161 %and1 = and i64 %shr, 7
162 %or = or i64 %and, %and1
[all...] |
| bitfield-insert.ll | 252 %and1 = and i32 %shr, 7
253 %or = or i32 %and, %and1
270 %and1 = and i32 %shr, 15
271 %or = or i32 %and, %and1
288 %and1 = and i32 %shr, 7
289 %or = or i32 %and, %and1
307 %and1 = and i32 %shr, 15
308 %or = or i32 %and, %and1
325 %and1 = and i32 %b, 65520 ; 0x0000fff0
326 %or = or i32 %and1, %an
[all...] |
| arm64-call-tailcalls.ll | 68 %and1 = and i32 %x, 2
69 %tobool2 = icmp eq i32 %and1, 0
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/Mips/ |
| fcopysign.ll | 14 ; CHECK-EL: and $[[AND1:[0-9]+]], $[[HI1]], $[[MSK1]]
16 ; CHECK-EL: or $[[OR:[0-9]+]], $[[AND0]], $[[AND1]]
27 ; CHECK-EB: and $[[AND1:[0-9]+]], $[[HI1]], $[[MSK1]]
28 ; CHECK-EB: or $[[OR:[0-9]+]], $[[AND0]], $[[AND1]]
|
| /external/llvm/test/CodeGen/X86/ |
| targetLoweringGeneric.ll | 26 %and1 = and i32 %add1, 1
27 %xor2 = xor i32 %and1, 1
|
| combine-or.ll | 85 %and1 = and <4 x i32> %a, <i32 -1, i32 -1, i32 0, i32 0>
87 %or = or <4 x i32> %and1, %and2
97 %and1 = and <2 x i64> %a, <i64 -1, i64 0>
99 %or = or <2 x i64> %and1, %and2
109 %and1 = and <4 x i32> %a, <i32 0, i32 0, i32 -1, i32 -1>
111 %or = or <4 x i32> %and1, %and2
121 %and1 = and <2 x i64> %a, <i64 0, i64 -1>
123 %or = or <2 x i64> %and1, %and2
133 %and1 = and <4 x i32> %a, <i32 -1, i32 0, i32 0, i32 0>
135 %or = or <4 x i32> %and1, %and
[all...] |
| /external/llvm/test/CodeGen/PowerPC/ |
| bperm.ll | 118 %and1 = shl i32 %x, 16
119 %shl = and i32 %and1, 16711680
231 %and1 = and i64 %shr, 15
232 %or = or i64 %and, %and1
245 %and1 = and i64 %shr, 15
247 %or = or i64 %and1, %and2
263 %and1 = and i64 %shr, 15
265 %or = or i64 %and1, %and2
|
| rm-zext.ll | 21 %and1 = shl i32 %x, 16
22 %shl = and i32 %and1, 16711680
|
| /external/llvm/test/Transforms/ConstantHoisting/ARM/ |
| const-addr-no-neg-offset.ll | 18 %and1 = and i32 %2, -17367041
19 store volatile i32 %and1, i32* inttoptr (i32 1073876996 to i32*), align 4096
|
| /external/swiftshader/third_party/LLVM/test/Transforms/InstCombine/ |
| bit-checks.ll | 275 %and1 = and i32 %argc2, %argc ; <i32> [#uses=1]
276 %tobool = icmp eq i32 %and1, %argc2 ; <i1> [#uses=1]
288 %and1 = and i32 %argc, %argc2 ; <i32> [#uses=1]
289 %tobool = icmp eq i32 %argc2, %and1 ; <i1> [#uses=1]
301 %and1 = and i32 %argc2, %argc ; <i32> [#uses=1]
302 %tobool = icmp eq i32 %argc2, %and1 ; <i1> [#uses=1]
317 %and1 = and i32 %argc, %bc ; <i32> [#uses=1]
318 %tobool = icmp eq i32 %and1, %bc ; <i1> [#uses=1]
333 %and1 = and i32 %bc, %argc ; <i32> [#uses=1]
334 %tobool = icmp eq i32 %and1, %bc ; <i1> [#uses=1
[all...] |
| /external/llvm/test/CodeGen/ARM/ |
| bfx.ll | 41 %and1 = lshr i32 %x, 16
42 %shr2 = and i32 %and1, 255
|
