| /external/vixl/test/aarch32/traces/ |
| assembler-cond-rd-rn-operand-rm-a32-ands.h | 38 0x0e, 0x40, 0x15, 0xd0 // ands le r4 r5 r14
41 0x0a, 0x50, 0x1b, 0xa0 // ands ge r5 r11 r10
44 0x09, 0x00, 0x19, 0x90 // ands ls r0 r9 r9
47 0x02, 0x80, 0x17, 0xd0 // ands le r8 r7 r2
50 0x0d, 0x10, 0x1a, 0x00 // ands eq r1 r10 r13
53 0x02, 0x90, 0x1c, 0xd0 // ands le r9 r12 r2
56 0x05, 0x60, 0x11, 0x50 // ands pl r6 r1 r5
59 0x06, 0x10, 0x1c, 0xa0 // ands ge r1 r12 r6
62 0x03, 0xd0, 0x1c, 0x30 // ands cc r13 r12 r3
65 0x09, 0x20, 0x14, 0xc0 // ands gt r2 r4 r
[all...] |
| assembler-cond-rd-rn-operand-rm-t32-ands.h | 38 0x19, 0xea, 0x0b, 0x0c // ands al r12 r9 r11
41 0x14, 0xea, 0x0a, 0x03 // ands al r3 r4 r10
44 0x10, 0xea, 0x0c, 0x02 // ands al r2 r0 r12
47 0x19, 0xea, 0x0d, 0x09 // ands al r9 r9 r13
50 0x12, 0xea, 0x04, 0x0b // ands al r11 r2 r4
53 0x13, 0xea, 0x07, 0x07 // ands al r7 r3 r7
56 0x16, 0xea, 0x09, 0x0b // ands al r11 r6 r9
59 0x17, 0xea, 0x0b, 0x08 // ands al r8 r7 r11
62 0x1c, 0xea, 0x0e, 0x0e // ands al r14 r12 r14
65 0x15, 0xea, 0x08, 0x08 // ands al r8 r5 r
[all...] |
| assembler-cond-rd-rn-operand-rm-shift-rs-a32-ands.h | 38 0x1a, 0x6c, 0x18, 0xe0 // ands al r6 r8 r10 LSL r12
41 0x16, 0x54, 0x1d, 0x80 // ands hi r5 r13 r6 LSL r4
44 0x7e, 0xb1, 0x10, 0x60 // ands vs r11 r0 r14 ROR r1
47 0x7b, 0x54, 0x10, 0x70 // ands vc r5 r0 r11 ROR r4
50 0x16, 0x91, 0x17, 0x00 // ands eq r9 r7 r6 LSL r1
53 0x3c, 0xc0, 0x19, 0x20 // ands cs r12 r9 r12 LSR r0
56 0x5d, 0xc3, 0x13, 0x40 // ands mi r12 r3 r13 ASR r3
59 0x30, 0xd1, 0x14, 0x60 // ands vs r13 r4 r0 LSR r1
62 0x13, 0x3d, 0x17, 0x30 // ands cc r3 r7 r3 LSL r13
65 0x11, 0xa6, 0x11, 0xd0 // ands le r10 r1 r1 LSL r
[all...] |
| assembler-cond-rd-rn-operand-const-a32-ands.h | 38 0xff, 0x97, 0x14, 0xd2 // ands le r9 r4 0x03fc0000
41 0xff, 0xeb, 0x13, 0x52 // ands pl r14 r3 0x0003fc00
44 0xff, 0x15, 0x16, 0x32 // ands cc r1 r6 0x3fc00000
47 0xab, 0x57, 0x11, 0x32 // ands cc r5 r1 0x02ac0000
50 0xab, 0xe2, 0x14, 0x52 // ands pl r14 r4 0xb000000a
53 0xff, 0x2b, 0x1d, 0x22 // ands cs r2 r13 0x0003fc00
56 0xab, 0xd5, 0x10, 0x42 // ands mi r13 r0 0x2ac00000
59 0xff, 0x0a, 0x10, 0x72 // ands vc r0 r0 0x000ff000
62 0xff, 0x2e, 0x19, 0x62 // ands vs r2 r9 0x00000ff0
65 0xff, 0xf0, 0x17, 0x32 // ands cc r15 r7 0x000000f
[all...] |
| assembler-cond-rd-rn-operand-const-t32-ands.h | 38 0x1e, 0xf0, 0x2b, 0x7d // ands al r13 r14 0x02ac0000
41 0x11, 0xf4, 0xab, 0x1a // ands al r10 r1 0x00156000
44 0x10, 0xf4, 0x7f, 0x7a // ands al r10 r0 0x000003fc
47 0x1b, 0xf0, 0x2b, 0x51 // ands al r1 r11 0x2ac00000
50 0x16, 0xf4, 0xab, 0x18 // ands al r8 r6 0x00156000
53 0x1c, 0xf4, 0x7f, 0x07 // ands al r7 r12 0x00ff0000
56 0x13, 0xf4, 0x7f, 0x0c // ands al r12 r3 0x00ff0000
59 0x17, 0xf4, 0x7f, 0x44 // ands al r4 r7 0x0000ff00
62 0x1d, 0xf0, 0x2b, 0x6b // ands al r11 r13 0x0ab00000
65 0x1c, 0xf0, 0xff, 0x26 // ands al r6 r12 0xff00ff0
[all...] |
| assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-ands.h | 38 0x80, 0xd2, 0x1d, 0x00 // ands eq r13 r13 r0 LSL 5
41 0x0d, 0xa5, 0x1e, 0x40 // ands mi r10 r14 r13 LSL 10
44 0x0d, 0x62, 0x12, 0x80 // ands hi r6 r2 r13 LSL 4
47 0x0d, 0x31, 0x15, 0xa0 // ands ge r3 r5 r13 LSL 2
50 0x61, 0xa5, 0x15, 0x30 // ands cc r10 r5 r1 ROR 10
53 0xe7, 0x33, 0x1e, 0xa0 // ands ge r3 r14 r7 ROR 7
56 0x87, 0xbb, 0x11, 0x50 // ands pl r11 r1 r7 LSL 23
59 0x84, 0x8a, 0x16, 0xd0 // ands le r8 r6 r4 LSL 21
62 0x82, 0x21, 0x19, 0x10 // ands ne r2 r9 r2 LSL 3
65 0x08, 0xe2, 0x1e, 0xa0 // ands ge r14 r14 r8 LSL
[all...] |
| assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-ands.h | 38 0x14, 0xea, 0xc7, 0x1c // ands al r12 r4 r7 LSL 7
41 0x18, 0xea, 0x7a, 0x57 // ands al r7 r8 r10 ROR 21
44 0x15, 0xea, 0x33, 0x35 // ands al r5 r5 r3 ROR 12
47 0x1d, 0xea, 0x8a, 0x5e // ands al r14 r13 r10 LSL 22
50 0x1a, 0xea, 0xbb, 0x09 // ands al r9 r10 r11 ROR 2
53 0x1b, 0xea, 0xc5, 0x3e // ands al r14 r11 r5 LSL 15
56 0x12, 0xea, 0x07, 0x72 // ands al r2 r2 r7 LSL 28
59 0x1b, 0xea, 0x71, 0x22 // ands al r2 r11 r1 ROR 9
62 0x12, 0xea, 0x08, 0x1b // ands al r11 r2 r8 LSL 4
65 0x1d, 0xea, 0x73, 0x06 // ands al r6 r13 r3 ROR
[all...] |
| assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-ands.h | 38 0xc7, 0xd2, 0x16, 0x00 // ands eq r13 r6 r7 ASR 5
41 0x48, 0x80, 0x1b, 0x40 // ands mi r8 r11 r8 ASR 32
44 0x4a, 0x29, 0x13, 0x80 // ands hi r2 r3 r10 ASR 18
47 0x2e, 0xd0, 0x18, 0x90 // ands ls r13 r8 r14 LSR 32
50 0xc2, 0x81, 0x19, 0x30 // ands cc r8 r9 r2 ASR 3
53 0x25, 0xe1, 0x12, 0x90 // ands ls r14 r2 r5 LSR 2
56 0xc1, 0x8f, 0x16, 0x50 // ands pl r8 r6 r1 ASR 31
59 0xae, 0x21, 0x10, 0xd0 // ands le r2 r0 r14 LSR 3
62 0xad, 0x27, 0x10, 0x10 // ands ne r2 r0 r13 LSR 15
65 0x23, 0x94, 0x1c, 0xa0 // ands ge r9 r12 r3 LSR
[all...] |
| assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-ands.h | 38 0x1d, 0xea, 0x6a, 0x2b // ands al r11 r13 r10 ASR 9
41 0x15, 0xea, 0xa2, 0x07 // ands al r7 r5 r2 ASR 2
44 0x12, 0xea, 0x5b, 0x15 // ands al r5 r2 r11 LSR 5
47 0x16, 0xea, 0x1a, 0x0e // ands al r14 r6 r10 LSR 32
50 0x16, 0xea, 0x53, 0x39 // ands al r9 r6 r3 LSR 13
53 0x14, 0xea, 0xd6, 0x7e // ands al r14 r4 r6 LSR 31
56 0x11, 0xea, 0x97, 0x32 // ands al r2 r1 r7 LSR 14
59 0x19, 0xea, 0x1c, 0x62 // ands al r2 r9 r12 LSR 24
62 0x1c, 0xea, 0xa4, 0x0a // ands al r10 r12 r4 ASR 2
65 0x1a, 0xea, 0x10, 0x26 // ands al r6 r10 r0 LSR
[all...] |
| /art/runtime/interpreter/mterp/arm/ |
| op_return_void.S | 5 ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST
|
| op_return_void_no_barrier.S | 3 ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST
|
| op_return.S | 11 ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST
|
| op_return_wide.S | 9 ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST
|
| /external/llvm/test/MC/AArch64/ |
| alias-logicalimm.s | 13 // CHECK: ands x0, x1, #0xfffffffffffffffd
14 // CHECK: ands x0, x1, #0xfffffffffffffffd
15 ands x0, x1, #~2
18 // CHECK: ands w0, w1, #0xfffffffd
19 // CHECK: ands w0, w1, #0xfffffffd
20 ands w0, w1, #~2
|
| arm64-logical-encoding.s | 13 ands w0, w0, #1
14 ands x0, x0, #1
15 ands w1, w2, #15
16 ands x1, x2, #15
23 ; CHECK: ands w0, w0, #0x1 ; encoding: [0x00,0x00,0x00,0x72]
24 ; CHECK: ands x0, x0, #0x1 ; encoding: [0x00,0x00,0x40,0xf2]
25 ; CHECK: ands w1, w2, #0xf ; encoding: [0x41,0x0c,0x00,0x72]
26 ; CHECK: ands x1, x2, #0xf ; encoding: [0x41,0x0c,0x40,0xf2]
72 ands w1, w2, w3
73 ands x1, x2, x
[all...] |
| /art/runtime/interpreter/mterp/arm64/ |
| op_return_void.S | 5 ands w7, w7, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST
|
| op_return_void_no_barrier.S | 3 ands w7, w7, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST
|
| op_return.S | 11 ands w7, w7, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST
|
| op_return_wide.S | 10 ands w7, w7, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/ARM/ |
| arm-and-tst-peephole.ll | 26 ; ARM: ands {{r[0-9]+}}, {{r[0-9]+}}, #3
30 ; THUMB-NEXT: ands r[[R0]], r
34 ; T2: ands {{r[0-9]+}}, {{r[0-9]+}}, #3
68 ; generates a predicated ANDS instruction. Check that the predicate is printed
81 ; ARM: ands
82 ; THUMB: ands
83 ; T2: ands
93 ; THUMB: ands
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| tcompat2.d | 13 0+04 <[^>]*> 4008 * ands r0, r1
14 0+06 <[^>]*> 4008 * ands r0, r1
|
| /bionic/libc/arch-arm/cortex-a15/bionic/ |
| __strcpy_chk.S | 48 ands r3, r1, #7
61 ands ip, r3, #2
76 ands ip, ip, #0x80808080
87 ands ip, ip, #0x80808080
92 ands ip, ip, #0x80808080
|
| /bionic/libc/arch-arm/cortex-a53/bionic/ |
| __strcpy_chk.S | 48 ands r3, r1, #7
61 ands ip, r3, #2
76 ands ip, ip, #0x80808080
87 ands ip, ip, #0x80808080
92 ands ip, ip, #0x80808080
|
| /bionic/libc/arch-arm/cortex-a7/bionic/ |
| __strcpy_chk.S | 48 ands r3, r1, #7
61 ands ip, r3, #2
76 ands ip, ip, #0x80808080
87 ands ip, ip, #0x80808080
92 ands ip, ip, #0x80808080
|
| /bionic/libc/arch-arm/denver/bionic/ |
| __strcpy_chk.S | 48 ands r3, r1, #7
61 ands ip, r3, #2
76 ands ip, ip, #0x80808080
87 ands ip, ip, #0x80808080
92 ands ip, ip, #0x80808080
|
