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Searched
full:b_hi
(Results
1 - 9
of
9
) sorted by null
/frameworks/rs/cpu_ref/
rsCpuIntrinsics_advsimd_YuvToRGB.S
37
* v6 out
B_hi
/ even
B_hi
accumulator
46
* v15
B_hi
luma tmp
53
* v22 odd
B_hi
accumulator
/art/compiler/optimizing/
intrinsics_mips.cc
1129
Register
b_hi
= locations->InAt(1).AsRegisterPairHigh<Register>();
local
1194
Register
b_hi
= locations->InAt(1).AsRegisterPairHigh<Register>();
local
[
all
...]
/external/llvm/test/CodeGen/AMDGPU/
llvm.amdgcn.div.scale.ll
277
; SI-DAG: s_load_dwordx2 s{{\[}}[[B_LO:[0-9]+]]:[[
B_HI
:[0-9]+]]{{\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0xd
279
; SI-DAG: v_mov_b32_e32 v[[VB_HI:[0-9]+]], s[[
B_HI
]]
/external/webp/src/dsp/
lossless_enc_sse2.c
584
const __m128i
B_hi
= _mm_unpackhi_epi32(*B, *A);
586
const __m128i s_hi = _mm_sad_epu8(A_hi,
B_hi
);
lossless_sse2.c
311
const __m128i
B_hi
= _mm_unpackhi_epi32(*B, *A);
313
const __m128i s_hi = _mm_sad_epu8(A_hi,
B_hi
);
/prebuilts/go/darwin-x86/src/cmd/vendor/golang.org/x/arch/arm/armasm/
tables.go
156
B_HI
[
all
...]
/prebuilts/go/linux-x86/src/cmd/vendor/golang.org/x/arch/arm/armasm/
tables.go
156
B_HI
[
all
...]
/prebuilts/go/darwin-x86/pkg/darwin_amd64/cmd/vendor/golang.org/x/arch/arm/
armasm.a
120
off n &err text·5 h?(ADC_EQ @% ADC_NE @%"ADC_CS @%|SADC_CC @%&ADC_MI @%(ADC_PL @%*ADC_VS @%,ADC_VC @%.ADC_HI @%0ADC_LS @%2ADC_GE @%4ADC_LT @%6ADC_GT @%8ADC_LE @%:ADC @%<ADC_ZZ @%>ADC_S_EQ @%@ADC_S_NE @%BADC_S_CS @%DADC_S_CC @%FADC_S_MI @%HADC_S_PL @%JADC_S_VS @%LADC_S_VC @%NADC_S_HI @%PADC_S_LS @%RADC_S_GE @%TADC_S_LT @%VADC_S_GT @%XADC_S_LE @%Z ADC_S @%\ADC_S_ZZ @%^ADD_EQ @%`ADD_NE @%bADD_CS @%dADD_CC @%fADD_MI @%hADD_PL @%jADD_VS @%lADD_VC @%nADD_HI @%pADD_LS @%rADD_GE @%tADD_LT @%vADD_GT @%xADD_LE @%zADD @%||ADD_ZZ @%~ADD_S_EQ @%?ADD_S_NE @%?ADD_S_CS @%?ADD_S_CC @%?ADD_S_MI @%?ADD_S_PL @%?ADD_S_VS @%?ADD_S_VC @%?ADD_S_HI @%?ADD_S_LS @%?ADD_S_GE @%?ADD_S_LT @%?ADD_S_GT @%?ADD_S_LE @%? ADD_S @%?ADD_S_ZZ @%?AND_EQ @%?AND_NE @%?AND_CS @%?AND_CC @%?AND_MI @%?AND_PL @%?AND_VS @%?AND_VC @%?AND_HI @%?AND_LS @%?AND_GE @%?AND_LT @%?AND_GT @%?AND_LE @%?AND @%?AND_ZZ @%?AND_S_EQ @%?AND_S_NE @%?AND_S_CS @%?AND_S_CC @%?AND_S_MI @%?AND_S_PL @%?AND_S_VS @%?AND_S_VC @%?AND_S_HI @%?AND_S_LS @%?AND_S_GE @%?AND_S_LT @%?AND_S_GT @%?AND_S_LE @%? AND_S @%?AND_S_ZZ @%?ASR_EQ @%?ASR_NE @%?ASR_CS @%?ASR_CC @%?ASR_MI @%?ASR_PL @%?ASR_VS @%?ASR_VC @%?ASR_HI @%?ASR_LS @%?ASR_GE @%?ASR_LT @%?ASR_GT @%?ASR_LE @%?ASR @%?ASR_ZZ @%?ASR_S_EQ @%?ASR_S_NE @%?ASR_S_CS @%?ASR_S_CC @%?ASR_S_MI @%?ASR_S_PL @%?ASR_S_VS @%?ASR_S_VC @%?ASR_S_HI @%?ASR_S_LS @%?ASR_S_GE @%?ASR_S_LT @%?ASR_S_GT @%?ASR_S_LE @%? ASR_S @%?ASR_S_ZZ @%?B_EQ @%?B_NE @%?B_CS @%?B_CC @%?B_MI @%?B_PL @%?B_VS @%?B_VC @%?
B_HI