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  /frameworks/rs/cpu_ref/
rsCpuIntrinsics_advsimd_YuvToRGB.S 33 * v2 out B_lo / even B_lo accumulator
44 * v13 B_lo luma tmp
49 * v18 odd B_lo accumulator
  /art/compiler/optimizing/
intrinsics_mips.cc 1128 Register b_lo = locations->InAt(1).AsRegisterPairLow<Register>(); local
1193 Register b_lo = locations->InAt(1).AsRegisterPairLow<Register>(); local
    [all...]
  /external/llvm/test/CodeGen/AMDGPU/
llvm.amdgcn.div.scale.ll 277 ; SI-DAG: s_load_dwordx2 s{{\[}}[[B_LO:[0-9]+]]:[[B_HI:[0-9]+]]{{\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0xd
278 ; SI-DAG: v_mov_b32_e32 v[[VB_LO:[0-9]+]], s[[B_LO]]
  /external/webp/src/dsp/
lossless_enc_sse2.c 582 const __m128i B_lo = _mm_unpacklo_epi32(*B, *A);
585 const __m128i s_lo = _mm_sad_epu8(A_lo, B_lo);
lossless_sse2.c 309 const __m128i B_lo = _mm_unpacklo_epi32(*B, *A);
312 const __m128i s_lo = _mm_sad_epu8(A_lo, B_lo);

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