/external/v8/src/x64/ |
codegen-x64.h | 39 Register base_reg, 44 : base_reg_(base_reg), 52 Register base_reg, 57 : base_reg_(base_reg), 65 Register base_reg, 70 : base_reg_(base_reg),
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/external/llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/ |
split-gep-and-gvn.ll | 48 ; PTX: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG:%(rd|r)[0-9]+]]{{\]}} 49 ; PTX: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG]]+4{{\]}} 50 ; PTX: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG]]+128{{\]}} 51 ; PTX: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG]]+132{{\]}} 91 ; PTX: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG:%(rd|r)[0-9]+]]{{\]}} 92 ; PTX: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG]]+4{{\]}} 93 ; PTX: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG]]+128{{\]}} 94 ; PTX: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG]]+132{{\]}} 141 ; PTX: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG:%(rd|r)[0-9]+]]{{\]}} 142 ; PTX: ld.shared.f32 {{%f[0-9]+}}, {{\[}}[[BASE_REG]]+4{{\]} [all...] |
/art/compiler/linker/arm64/ |
relative_patcher_arm64.h | 35 static uint32_t EncodeBakerReadBarrierFieldData(uint32_t base_reg, uint32_t holder_reg) { 36 CheckValidReg(base_reg); 39 BakerReadBarrierFirstRegField::Encode(base_reg) |
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relative_patcher_arm64.cc | 314 // LDR (immediate) with correct base_reg. 316 CHECK_EQ(next_insn & 0xffc003e0u, 0xb9400000u | (key.GetOffsetParams().base_reg << 5)); 347 params.offset_params.base_reg = BakerReadBarrierFirstRegField::Decode(value); 348 CheckValidReg(params.offset_params.base_reg); 376 vixl::aarch64::Register base_reg, 397 __ Add(base_reg, base_reg, Operand(vixl::aarch64::ip0, LSR, 32)); 423 auto base_reg = Register::GetXRegFromCode(key.GetOffsetParams().base_reg); local 426 // If base_reg differs from holder_reg, the offset was too large and we must hav [all...] |
relative_patcher_arm64_test.cc | 466 std::vector<uint8_t> CompileBakerOffsetThunk(uint32_t base_reg, uint32_t holder_reg) { 468 0u, Arm64RelativePatcher::EncodeBakerReadBarrierFieldData(base_reg, holder_reg)); [all...] |
/external/mesa3d/src/mesa/program/ |
register_allocate.c | 210 * Adds a conflict between base_reg and reg, and also between reg and 211 * anything that base_reg conflicts with. 219 unsigned int base_reg, unsigned int reg) 223 ra_add_reg_conflict(regs, reg, base_reg); 225 for (i = 0; i < regs->regs[base_reg].num_conflicts; i++) { 226 ra_add_reg_conflict(regs, reg, regs->regs[base_reg].conflict_list[i]);
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register_allocate.h | 44 unsigned int base_reg, unsigned int reg);
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/external/mesa3d/src/mesa/drivers/dri/i965/ |
brw_vec4_reg_allocate.cpp | 131 for (int base_reg = j; 132 base_reg < j + class_sizes[i]; 133 base_reg++) { 134 ra_add_transitive_reg_conflict(brw->vs.regs, base_reg, reg);
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brw_fs_reg_allocate.cpp | 119 for (int base_reg = j; 120 base_reg < j + class_sizes[i]; 121 base_reg++) { 122 ra_add_transitive_reg_conflict(brw->wm.regs, base_reg, reg);
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/toolchain/binutils/binutils-2.25/opcodes/ |
metag-dis.c | 472 const char *base_reg; local 481 base_reg = lookup_reg_name (base_unit, base_no); 491 snprintf (buf, buf_size, "[%s]", base_reg); 498 snprintf (buf, buf_size, "[%s++]", base_reg); 500 snprintf (buf, buf_size, "[++%s]", base_reg); 507 snprintf (buf, buf_size, "[%s--]", base_reg); 509 snprintf (buf, buf_size, "[--%s]", base_reg); 519 snprintf (buf, buf_size, "[%s+#%d++]", base_reg, offset); 521 snprintf (buf, buf_size, "[%s++#%d]", base_reg, offset); 524 snprintf (buf, buf_size, "[%s+#%d]", base_reg, offset) 552 const char *base_reg; local 582 const char *base_reg; local 598 const char *base_reg; local 614 const char *base_reg; local 909 const char *base_reg; local 2330 const char *base_reg = "?"; local [all...] |
/toolchain/binutils/binutils-2.25/gas/config/ |
tc-metag.c | 186 const metag_reg *base_reg; member in struct:__anon108273 736 if (regs[0]->unit != addr->base_reg->unit) 768 addr->base_reg = regs[0]; 1063 (regs[0]->unit == addr.base_reg->unit || 1064 (size == 8 && is_unit_pair (regs[0], addr.base_reg)))) 1087 if (!is_short_unit (addr.base_reg->unit)) 1093 insn->bits |= ((addr.base_reg->no << 14) | 1094 ((addr.base_reg->unit & SHORT_UNIT_MASK) << 5)); 1188 if (!is_short_unit (addr.base_reg->unit)) 1194 if (addr.base_reg->no > 1 [all...] |
tc-tic6x.c | 1143 tic6x_register base_reg; member in struct:__anon108333 1425 tic6x_register base_reg; local [all...] |
tc-i386.c | 311 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode 313 const reg_entry *base_reg; member in struct:_i386_insn [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/X86/ |
X86ISelDAGToDAG.cpp | 60 SDValue Base_Reg; 86 return IndexReg.getNode() != 0 || Base_Reg.getNode() != 0; 94 dyn_cast_or_null<RegisterSDNode>(Base_Reg.getNode())) 101 Base_Reg = Reg; 106 dbgs() << "Base_Reg "; 107 if (Base_Reg.getNode() != 0) 108 Base_Reg.getNode()->dump(); 235 AM.Base_Reg; 707 AM.Base_Reg.getNode() == 0) { 708 AM.Base_Reg = AM.IndexReg [all...] |
/art/compiler/linker/arm/ |
relative_patcher_arm_base.h | 51 uint32_t base_reg; // Base register, different from holder for large offset. member in struct:art::linker::ArmBaseRelativePatcher::BakerReadBarrierOffsetParams
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/device/linaro/bootloader/edk2/ArmPlatformPkg/Scripts/Ds5/ |
cmd_load_symbols.py | 40 base_reg = re.compile("(.*)")
variable
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/external/llvm/lib/Target/X86/ |
X86ISelDAGToDAG.cpp | 58 SDValue Base_Reg; 86 IndexReg.getNode() != nullptr || Base_Reg.getNode() != nullptr; 93 dyn_cast_or_null<RegisterSDNode>(Base_Reg.getNode())) 100 Base_Reg = Reg; 106 dbgs() << "Base_Reg "; 107 if (Base_Reg.getNode()) 108 Base_Reg.getNode()->dump(); 252 : AM.Base_Reg; 846 AM.Base_Reg.getNode() == nullptr) { 847 AM.Base_Reg = AM.IndexReg [all...] |
/toolchain/binutils/binutils-2.25/include/elf/ |
s390.h | 31 #define BASE_REG 13 /* Global Base reg */
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/external/mesa3d/src/mesa/drivers/dri/radeon/ |
radeon_state_init.c | 423 uint32_t base_reg; local 435 case 1: base_reg = RADEON_PP_CUBIC_OFFSET_T1_0; break; 436 case 2: base_reg = RADEON_PP_CUBIC_OFFSET_T2_0; break; 438 case 0: base_reg = RADEON_PP_CUBIC_OFFSET_T0_0; break; 444 OUT_BATCH(CP_PACKET0(base_reg + (4 * j), 0)); [all...] |
/art/compiler/optimizing/ |
code_generator_mips64.cc | [all...] |
code_generator_mips.cc | [all...] |
code_generator_arm.h | 468 // MOVW+MOVT to load the offset to base_reg and then ADD base_reg, PC. The offset
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/art/compiler/utils/arm/ |
assembler_thumb2.h | 261 void vldmiad(Register base_reg, DRegister reg, int nregs, Condition cond = AL) OVERRIDE; 262 void vstmiad(Register base_reg, DRegister reg, int nregs, Condition cond = AL) OVERRIDE; 380 // Emit an ADR (or a sequence of instructions) to load the jump table address into base_reg. This 382 JumpTable* CreateJumpTable(std::vector<Label*>&& labels, Register base_reg) OVERRIDE; [all...] |
assembler_arm.h | 646 virtual void vldmiad(Register base_reg, DRegister reg, int nregs, Condition cond = AL) = 0; 647 virtual void vstmiad(Register base_reg, DRegister reg, int nregs, Condition cond = AL) = 0; 909 virtual JumpTable* CreateJumpTable(std::vector<Label*>&& labels, Register base_reg) = 0; [all...] |
/art/compiler/utils/mips/ |
assembler_mips.h | 809 // (for R6 only; base_reg must be ZERO). To be used with data labels in the literal / 811 void LoadLabelAddress(Register dest_reg, Register base_reg, MipsLabel* label); 817 // (for R6 only; base_reg must be ZERO). 818 void LoadLiteral(Register dest_reg, Register base_reg, Literal* literal); [all...] |