| /external/llvm/test/MC/Disassembler/Mips/mips32r6/ |
| valid-xfail-mips32r6.txt | 10 0x20 0xc0 0x00 0x40 # CHECK: beqc $6, $zero, 256
11 0x20 0xa0 0x00 0x40 # CHECK: beqc $5, $zero, 256
12 0x20 0xa6 0x00 0x40 # CHECK: beqc $5, $6, 256
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r6/ |
| valid-xfail-mips64r6.txt | 10 0x20 0xc0 0x00 0x40 # CHECK: beqc $6, $zero, 260
11 0x20 0xa0 0x00 0x40 # CHECK: beqc $5, $zero, 260
12 0x20 0xa6 0x00 0x40 # CHECK: beqc $5, $6, 260
|
| /art/runtime/interpreter/mterp/mips64/ |
| bincmp.S | 16 beqc rPROFILE, v0, .L_check_not_taken_osr
|
| zcmp.S | 14 beqc rPROFILE, v0, .L_check_not_taken_osr
|
| footer.S | 102 beqc rPROFILE, v0, .L_osr_check
139 beqc rPROFILE, v0, .L_check_osr_forward
|
| /external/llvm/test/CodeGen/Mips/compactbranches/ |
| no-beqzc-bnezc.ll | 37 ; beqc and bnec have the restriction that $rs < $rt.
41 ; ENCODING-NOT: beqc $5, $4
|
| beqc-bnec-register-constraint.ll | 3 ; beqc/bnec have the constraint that $rs < $rt && $rs != 0 && $rt != 0
36 ; CHECK-NOT: beqc $[[R1:[0-9]+]], $[[R1]]
|
| compact-branches.ll | 41 ; CHECK beqc
|
| /external/llvm/test/MC/Mips/mips32r6/ |
| relocations.s | 11 # CHECK-FIXUP: beqc $5, $6, bar # encoding: [0x20,0xa6,A,A]
61 beqc $5, $6, bar
|
| valid.s | 36 # beqc requires rs < rt && rs != 0 but we accept this and fix it. See also bovc.
37 beqc $5, $6, 256 # CHECK: beqc $5, $6, 256 # encoding: [0x20,0xa6,0x00,0x40]
38 beqc $6, $5, 256 # CHECK: beqc $6, $5, 256 # encoding: [0x20,0xa6,0x00,0x40]
63 # bovc requires that rs >= rt but we accept both and fix this. See also beqc.
|
| invalid.s | 52 beqc $0, $2, local_label # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction
58 beqc $2, $2, local_label # CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| r6.s | 136 beqc $3, $2, ext
137 beqc $2, $3, ext
138 beqc $3, $2, . + 4 + (-32768 << 2)
139 beqc $3, $2, . + 4 + (32767 << 2)
140 beqc $3, $2, 1f
|
| r6-n32.d | 199 0+0278 <[^>]*> 20430000 beqc v0,v1,0000027c <[^>]*>
202 0+0280 <[^>]*> 20430000 beqc v0,v1,00000284 <[^>]*>
205 0+0288 <[^>]*> 20430000 beqc v0,v1,0000028c <[^>]*>
208 0+0290 <[^>]*> 20430000 beqc v0,v1,00000294 <[^>]*>
211 0+0298 <[^>]*> 20430000 beqc v0,v1,0000029c <[^>]*>
|
| r6.d | 198 0+0278 <[^>]*> 2043ffff beqc v0,v1,00000278 <[^>]*>
201 0+0280 <[^>]*> 2043ffff beqc v0,v1,00000280 <[^>]*>
204 0+0288 <[^>]*> 20438000 beqc v0,v1,fffe028c <[^>]*>
207 0+0290 <[^>]*> 20437fff beqc v0,v1,00020290 <[^>]*>
210 0+0298 <[^>]*> 2043ffff beqc v0,v1,00000298 <[^>]*>
|
| r6-n64.d | 259 0+0278 <[^>]*> 20430000 beqc v0,v1,0+027c <[^>]*>
264 0+0280 <[^>]*> 20430000 beqc v0,v1,0+0284 <[^>]*>
269 0+0288 <[^>]*> 20430000 beqc v0,v1,0+028c <[^>]*>
274 0+0290 <[^>]*> 20430000 beqc v0,v1,0+0294 <[^>]*>
279 0+0298 <[^>]*> 20430000 beqc v0,v1,0+029c <[^>]*>
|
| /art/compiler/optimizing/ |
| optimizing_cfi_test.cc | 272 __ Beqc(mips64::A1, mips64::A2, &target);
273 // Push the target out of range of BEQC.
|
| /external/llvm/test/MC/Mips/mips64r6/ |
| relocations.s | 11 # CHECK-FIXUP: beqc $5, $6, bar # encoding: [0x20,0xa6,A,A]
66 beqc $5, $6, bar
|
| valid.s | 36 # beqc requires rs < rt && rs != 0 but we accept this and fix it. See also bovc.
37 beqc $5, $6, 256 # CHECK: beqc $5, $6, 256 # encoding: [0x20,0xa6,0x00,0x40]
38 beqc $6, $5, 256 # CHECK: beqc $6, $5, 256 # encoding: [0x20,0xa6,0x00,0x40]
63 # bovc requires that rs >= rt but we accept both and fix this. See also beqc.
|
| invalid.s | 48 beqc $0, $2, local_label # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction
54 beqc $2, $2, local_label # CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different
|
| /external/llvm/lib/Target/Mips/ |
| MipsHazardSchedule.cpp | 27 /// 0x8008 beqc a1,a2,<P+0x54>
|
| MipsSEInstrInfo.cpp | 428 case Mips::BEQC: return Mips::BNEC;
429 case Mips::BNEC: return Mips::BEQC;
515 Opc == Mips::BEQC || Opc == Mips::BNEC || Opc == Mips::BLTC ||
|
| MipsInstrInfo.cpp | 308 return Mips::BEQC;
415 case Mips::BEQC:
|
| /external/v8/src/ic/mips/ |
| ic-mips.cc | 626 opcode == POP10 || // BEQC
635 opcode = POP30; // change BEQC to BNEC.
644 opcode = POP10; // change BNEC to BEQC.
|
| /external/v8/src/ic/mips64/ |
| ic-mips64.cc | 627 opcode == POP10 || // BEQC
636 opcode = POP30; // change BEQC to BNEC.
645 opcode = POP10; // change BNEC to BEQC.
|
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsMCCodeEmitter.cpp | 121 // Fix a bad compact branch encoding for beqc/bnec.
132 if (Inst.getOpcode() == Mips::BNEC || Inst.getOpcode() == Mips::BEQC) {
211 case Mips::BEQC:
[all...] |
