| /external/vixl/test/aarch32/traces/ |
| assembler-cond-rd-rn-operand-rm-a32-bics.h | 38 0x0e, 0x40, 0xd5, 0xd1 // bics le r4 r5 r14
41 0x0a, 0x50, 0xdb, 0xa1 // bics ge r5 r11 r10
44 0x09, 0x00, 0xd9, 0x91 // bics ls r0 r9 r9
47 0x02, 0x80, 0xd7, 0xd1 // bics le r8 r7 r2
50 0x0d, 0x10, 0xda, 0x01 // bics eq r1 r10 r13
53 0x02, 0x90, 0xdc, 0xd1 // bics le r9 r12 r2
56 0x05, 0x60, 0xd1, 0x51 // bics pl r6 r1 r5
59 0x06, 0x10, 0xdc, 0xa1 // bics ge r1 r12 r6
62 0x03, 0xd0, 0xdc, 0x31 // bics cc r13 r12 r3
65 0x09, 0x20, 0xd4, 0xc1 // bics gt r2 r4 r
[all...] |
| assembler-cond-rd-rn-operand-rm-t32-bics.h | 38 0x39, 0xea, 0x0b, 0x0c // bics al r12 r9 r11
41 0x34, 0xea, 0x0a, 0x03 // bics al r3 r4 r10
44 0x30, 0xea, 0x0c, 0x02 // bics al r2 r0 r12
47 0x39, 0xea, 0x0d, 0x09 // bics al r9 r9 r13
50 0x32, 0xea, 0x04, 0x0b // bics al r11 r2 r4
53 0x33, 0xea, 0x07, 0x07 // bics al r7 r3 r7
56 0x36, 0xea, 0x09, 0x0b // bics al r11 r6 r9
59 0x37, 0xea, 0x0b, 0x08 // bics al r8 r7 r11
62 0x3c, 0xea, 0x0e, 0x0e // bics al r14 r12 r14
65 0x35, 0xea, 0x08, 0x08 // bics al r8 r5 r
[all...] |
| assembler-cond-rd-rn-operand-rm-shift-rs-a32-bics.h | 38 0x1a, 0x6c, 0xd8, 0xe1 // bics al r6 r8 r10 LSL r12
41 0x16, 0x54, 0xdd, 0x81 // bics hi r5 r13 r6 LSL r4
44 0x7e, 0xb1, 0xd0, 0x61 // bics vs r11 r0 r14 ROR r1
47 0x7b, 0x54, 0xd0, 0x71 // bics vc r5 r0 r11 ROR r4
50 0x16, 0x91, 0xd7, 0x01 // bics eq r9 r7 r6 LSL r1
53 0x3c, 0xc0, 0xd9, 0x21 // bics cs r12 r9 r12 LSR r0
56 0x5d, 0xc3, 0xd3, 0x41 // bics mi r12 r3 r13 ASR r3
59 0x30, 0xd1, 0xd4, 0x61 // bics vs r13 r4 r0 LSR r1
62 0x13, 0x3d, 0xd7, 0x31 // bics cc r3 r7 r3 LSL r13
65 0x11, 0xa6, 0xd1, 0xd1 // bics le r10 r1 r1 LSL r
[all...] |
| assembler-cond-rd-rn-operand-const-a32-bics.h | 38 0xff, 0x97, 0xd4, 0xd3 // bics le r9 r4 0x03fc0000
41 0xff, 0xeb, 0xd3, 0x53 // bics pl r14 r3 0x0003fc00
44 0xff, 0x15, 0xd6, 0x33 // bics cc r1 r6 0x3fc00000
47 0xab, 0x57, 0xd1, 0x33 // bics cc r5 r1 0x02ac0000
50 0xab, 0xe2, 0xd4, 0x53 // bics pl r14 r4 0xb000000a
53 0xff, 0x2b, 0xdd, 0x23 // bics cs r2 r13 0x0003fc00
56 0xab, 0xd5, 0xd0, 0x43 // bics mi r13 r0 0x2ac00000
59 0xff, 0x0a, 0xd0, 0x73 // bics vc r0 r0 0x000ff000
62 0xff, 0x2e, 0xd9, 0x63 // bics vs r2 r9 0x00000ff0
65 0xff, 0xf0, 0xd7, 0x33 // bics cc r15 r7 0x000000f
[all...] |
| assembler-cond-rd-rn-operand-const-t32-bics.h | 38 0x3e, 0xf0, 0x2b, 0x7d // bics al r13 r14 0x02ac0000
41 0x31, 0xf4, 0xab, 0x1a // bics al r10 r1 0x00156000
44 0x30, 0xf4, 0x7f, 0x7a // bics al r10 r0 0x000003fc
47 0x3b, 0xf0, 0x2b, 0x51 // bics al r1 r11 0x2ac00000
50 0x36, 0xf4, 0xab, 0x18 // bics al r8 r6 0x00156000
53 0x3c, 0xf4, 0x7f, 0x07 // bics al r7 r12 0x00ff0000
56 0x33, 0xf4, 0x7f, 0x0c // bics al r12 r3 0x00ff0000
59 0x37, 0xf4, 0x7f, 0x44 // bics al r4 r7 0x0000ff00
62 0x3d, 0xf0, 0x2b, 0x6b // bics al r11 r13 0x0ab00000
65 0x3c, 0xf0, 0xff, 0x26 // bics al r6 r12 0xff00ff0
[all...] |
| assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32-bics.h | 38 0x80, 0xd2, 0xdd, 0x01 // bics eq r13 r13 r0 LSL 5
41 0x0d, 0xa5, 0xde, 0x41 // bics mi r10 r14 r13 LSL 10
44 0x0d, 0x62, 0xd2, 0x81 // bics hi r6 r2 r13 LSL 4
47 0x0d, 0x31, 0xd5, 0xa1 // bics ge r3 r5 r13 LSL 2
50 0x61, 0xa5, 0xd5, 0x31 // bics cc r10 r5 r1 ROR 10
53 0xe7, 0x33, 0xde, 0xa1 // bics ge r3 r14 r7 ROR 7
56 0x87, 0xbb, 0xd1, 0x51 // bics pl r11 r1 r7 LSL 23
59 0x84, 0x8a, 0xd6, 0xd1 // bics le r8 r6 r4 LSL 21
62 0x82, 0x21, 0xd9, 0x11 // bics ne r2 r9 r2 LSL 3
65 0x08, 0xe2, 0xde, 0xa1 // bics ge r14 r14 r8 LSL
[all...] |
| assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32-bics.h | 38 0x34, 0xea, 0xc7, 0x1c // bics al r12 r4 r7 LSL 7
41 0x38, 0xea, 0x7a, 0x57 // bics al r7 r8 r10 ROR 21
44 0x35, 0xea, 0x33, 0x35 // bics al r5 r5 r3 ROR 12
47 0x3d, 0xea, 0x8a, 0x5e // bics al r14 r13 r10 LSL 22
50 0x3a, 0xea, 0xbb, 0x09 // bics al r9 r10 r11 ROR 2
53 0x3b, 0xea, 0xc5, 0x3e // bics al r14 r11 r5 LSL 15
56 0x32, 0xea, 0x07, 0x72 // bics al r2 r2 r7 LSL 28
59 0x3b, 0xea, 0x71, 0x22 // bics al r2 r11 r1 ROR 9
62 0x32, 0xea, 0x08, 0x1b // bics al r11 r2 r8 LSL 4
65 0x3d, 0xea, 0x73, 0x06 // bics al r6 r13 r3 ROR
[all...] |
| assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32-bics.h | 38 0xc7, 0xd2, 0xd6, 0x01 // bics eq r13 r6 r7 ASR 5
41 0x48, 0x80, 0xdb, 0x41 // bics mi r8 r11 r8 ASR 32
44 0x4a, 0x29, 0xd3, 0x81 // bics hi r2 r3 r10 ASR 18
47 0x2e, 0xd0, 0xd8, 0x91 // bics ls r13 r8 r14 LSR 32
50 0xc2, 0x81, 0xd9, 0x31 // bics cc r8 r9 r2 ASR 3
53 0x25, 0xe1, 0xd2, 0x91 // bics ls r14 r2 r5 LSR 2
56 0xc1, 0x8f, 0xd6, 0x51 // bics pl r8 r6 r1 ASR 31
59 0xae, 0x21, 0xd0, 0xd1 // bics le r2 r0 r14 LSR 3
62 0xad, 0x27, 0xd0, 0x11 // bics ne r2 r0 r13 LSR 15
65 0x23, 0x94, 0xdc, 0xa1 // bics ge r9 r12 r3 LSR
[all...] |
| assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32-bics.h | 38 0x3d, 0xea, 0x6a, 0x2b // bics al r11 r13 r10 ASR 9
41 0x35, 0xea, 0xa2, 0x07 // bics al r7 r5 r2 ASR 2
44 0x32, 0xea, 0x5b, 0x15 // bics al r5 r2 r11 LSR 5
47 0x36, 0xea, 0x1a, 0x0e // bics al r14 r6 r10 LSR 32
50 0x36, 0xea, 0x53, 0x39 // bics al r9 r6 r3 LSR 13
53 0x34, 0xea, 0xd6, 0x7e // bics al r14 r4 r6 LSR 31
56 0x31, 0xea, 0x97, 0x32 // bics al r2 r1 r7 LSR 14
59 0x39, 0xea, 0x1c, 0x62 // bics al r2 r9 r12 LSR 24
62 0x3c, 0xea, 0xa4, 0x0a // bics al r10 r12 r4 ASR 2
65 0x3a, 0xea, 0x10, 0x26 // bics al r6 r10 r0 LSR
[all...] |
| /external/llvm/test/CodeGen/Thumb/ |
| bic_imm.ll | 8 ; CHECK-T1: bics r0, r1
10 ; CHECK-T2: bics r0, r1
20 ; CHECK-T1: bics r0, r1
|
| /bionic/libc/arch-arm/generic/bionic/ |
| strlen.c | 69 "bics %[t], %[t], %[v] \n"
76 "bics %[t], %[t], %[v] \n"
82 "bics %[t], %[t], %[v] \n"
88 "bics %[t], %[t], %[v] \n"
94 "bics %[t], %[t], %[v] \n"
100 "bics %[t], %[t], %[v] \n"
106 "bics %[t], %[t], %[v] \n"
112 "bics %[t], %[t], %[v] \n"
|
| strcpy.S | 55 bics r2, r2, r3
69 bics r2, r2, r3
74 bics r2, r2, r4
|
| /external/llvm/test/MC/AArch64/ |
| alias-logicalimm.s | 16 bics x0, x1, #2
21 bics w0, w1, #2
|
| arm64-logical-encoding.s | 116 bics w1, w2, w3
117 bics x1, x2, x3
118 bics w1, w2, w3, lsl #3
119 bics x1, x2, x3, lsl #3
120 bics w1, w2, w3, lsr #3
121 bics x1, x2, x3, lsr #3
122 bics w1, w2, w3, asr #3
123 bics x1, x2, x3, asr #3
124 bics w1, w2, w3, ror #3
125 bics x1, x2, x3, ror #
[all...] |
| /external/llvm/test/CodeGen/Thumb2/ |
| thumb2-bic.ll | 5 ; CHECK: bics r0, r1
13 ; CHECK: bics r0, r1
21 ; CHECK: bics r0, r1
29 ; CHECK: bics r0, r1
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/Thumb2/ |
| thumb2-bic.ll | 5 ; CHECK: bics r0, r1
13 ; CHECK: bics r0, r1
21 ; CHECK: bics r0, r1
29 ; CHECK: bics r0, r1
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| armv1.s | 23 bics r0, r0, r0
|
| tcompat2.d | 21 0+14 <[^>]*> 4388 * bics r0, r1
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| arm64-logical.txt | 126 # CHECK: bics w1, w2, w3
127 # CHECK: bics x1, x2, x3
128 # CHECK: bics w1, w2, w3, lsl #3
129 # CHECK: bics x1, x2, x3, lsl #3
130 # CHECK: bics w1, w2, w3, lsr #3
131 # CHECK: bics x1, x2, x3, lsr #3
132 # CHECK: bics w1, w2, w3, asr #3
133 # CHECK: bics x1, x2, x3, asr #3
134 # CHECK: bics w1, w2, w3, ror #3
135 # CHECK: bics x1, x2, x3, ror #
[all...] |
| /external/llvm/test/MC/ARM/ |
| thumb_rewrites.s | 98 bics r0, r0, r1
99 @ CHECK: bics r0, r1 @ encoding: [0x88,0x43]
|
| thumb2-narrow-dp.ll | [all...] |
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| arm_instructions.s | 45 @ CHECK: bics r1, r2, r3 @ encoding: [0x03,0x10,0xd2,0xe1]
46 bics r1,r2,r3
|
| /external/vixl/test/aarch32/config/ |
| cond-rd-rn-operand-const-a32.json | 39 "Bics", // BICS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
|
| cond-rd-rn-operand-const-t32.json | 45 "Bics", // BICS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T1
|
| /bionic/libc/arch-arm64/generic/bionic/ |
| strlen.S | 115 bics has_nul1, tmp1, tmp2
155 bics has_nul1, tmp1, tmp2
189 bics has_nul1, tmp1, tmp2
198 bics has_nul1, tmp1, tmp2
|
