| /device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Include/Omap3530/ |
| Omap3530Usb.h | 29 #define UHH_SYSCONFIG_ENAWAKEUP_ENABLE BIT2
39 #define UHH_HOSTCONFIG_ENA_INCR4_ENABLE BIT2
43 #define UHH_SYSSTATUS_RESETDONE (BIT0 | BIT1 | BIT2)
|
| Omap3530Prcm.h | 55 #define CM_FCLKEN3_CORE_EN_USBTLL_MASK BIT2
57 #define CM_FCLKEN3_CORE_EN_USBTLL_ENABLE BIT2
63 #define CM_ICLKEN3_CORE_EN_USBTLL_MASK BIT2
65 #define CM_ICLKEN3_CORE_EN_USBTLL_ENABLE BIT2
156 #define CM_CLKSEL_PER_CLKSEL_GPT4_SYS BIT2
160 #define RST_DPLL3 BIT2
|
| Omap3530Timer.h | 54 #define TISR_TCAR_IT_FLAG_MASK BIT2
64 #define TISR_TCAR_IT_FLAG_CLEAR BIT2
74 #define TIER_TCAR_IT_ENABLE (BIT2
|
| Omap3530Uart.h | 32 #define UART_FCR_TX_FIFO_CLEAR BIT2
50 // BIT2:BIT0
|
| Omap3530.h | 35 #define PBIASSPEEDCTRL0 BIT2
|
| Omap3530I2c.h | 24 #define ARDY_IE BIT2
31 #define ARDY BIT2
|
| /device/linaro/bootloader/edk2/Omap35xxPkg/Include/Omap3530/ |
| Omap3530Usb.h | 29 #define UHH_SYSCONFIG_ENAWAKEUP_ENABLE BIT2
39 #define UHH_HOSTCONFIG_ENA_INCR4_ENABLE BIT2
43 #define UHH_SYSSTATUS_RESETDONE (BIT0 | BIT1 | BIT2)
|
| Omap3530Prcm.h | 55 #define CM_FCLKEN3_CORE_EN_USBTLL_MASK BIT2
57 #define CM_FCLKEN3_CORE_EN_USBTLL_ENABLE BIT2
63 #define CM_ICLKEN3_CORE_EN_USBTLL_MASK BIT2
65 #define CM_ICLKEN3_CORE_EN_USBTLL_ENABLE BIT2
156 #define CM_CLKSEL_PER_CLKSEL_GPT4_SYS BIT2
160 #define RST_DPLL3 BIT2
|
| Omap3530Timer.h | 54 #define TISR_TCAR_IT_FLAG_MASK BIT2
64 #define TISR_TCAR_IT_FLAG_CLEAR BIT2
74 #define TIER_TCAR_IT_ENABLE (BIT2
|
| Omap3530Uart.h | 32 #define UART_FCR_TX_FIFO_CLEAR BIT2
50 // BIT2:BIT0
|
| Omap3530.h | 35 #define PBIASSPEEDCTRL0 BIT2
|
| Omap3530I2c.h | 24 #define ARDY_IE BIT2
31 #define ARDY BIT2
|
| /device/linaro/bootloader/edk2/EmbeddedPkg/Drivers/Isp1761UsbDxe/ |
| Isp1761UsbDxe.h | 44 #define ISP1761_DC_INTERRUPT_PSOF BIT2
65 #define ISP1761_MODE_WKUPCS BIT2
75 #define ISP1761_INTERRUPT_CONFIG_ACK_ONLY BIT2 | BIT5 | BIT6
82 #define ISP1761_CTRL_FUNCTION_DSEN BIT2
98 #define ISP1761_OTG_CTRL_DM_PULLDOWN BIT2
|
| /external/swiftshader/third_party/LLVM/test/Transforms/MemCpyOpt/ |
| 2011-06-02-CallSlotOverwritten.ll | 26 %bit2 = bitcast %struct2* %y to i64*
28 store i64 %load, i64* %bit2, align 8
31 ; CHECK: store i64 %load, i64* %bit2, align 8
|
| /device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/ |
| PchRegsPcu.h | 83 #define B_PCH_LPC_COMMAND_BME BIT2 // Bus Master Enable
147 #define B_PCH_LPC_PMC_BASE_ADDRNG BIT2 // Address Range
159 #define B_PCH_LPC_IO_BASE_ADDRNG BIT2 // Address Range
166 #define B_PCH_LPC_ILB_BASE_ADDRNG BIT2 // Address Range
173 #define B_PCH_LPC_SPI_BASE_ADDRNG BIT2 // Address Range
180 #define B_PCH_LPC_MPHY_BASE_ADDRNG BIT2 // Address Range
187 #define B_PCH_LPC_PUNIT_BASE_ADDRNG BIT2 // Address Range
206 #define B_PCH_LPC_FWH_BIOS_DEC_E60 BIT2 // 60-6F Enable
250 #define B_PCH_ILB_ACPI_CNT_SCI_IRQ_SEL (BIT2 | BIT1 | BIT0) // SCI IRQ Select
254 #define V_PCH_ILB_ACPI_CNT_SCI_IRQ_20 BIT2 // IRQ20 (Only if APIC enabled)
[all...] |
| PchRegsLpss.h | 67 #define B_PCH_LPSS_DMAC_STSCMD_BME BIT2 // Bus Master Enable
86 #define B_PCH_LPSS_DMAC_BAR_TYPE (BIT2 | BIT1) // Type
93 #define B_PCH_LPSS_DMAC_BAR1_TYPE (BIT2 | BIT1) // Type
152 #define B_PCH_LPSS_I2C_STSCMD_BME BIT2 // Bus Master Enable
171 #define B_PCH_LPSS_I2C_BAR_TYPE (BIT2 | BIT1) // Type
178 #define B_PCH_LPSS_I2C_BAR1_TYPE (BIT2 | BIT1) // Type
239 #define B_PCH_LPSS_PWM_STSCMD_BME BIT2 // Bus Master Enable
258 #define B_PCH_LPSS_PWM_BAR_TYPE (BIT2 | BIT1) // Type
265 #define B_PCH_LPSS_PWM_BAR1_TYPE (BIT2 | BIT1) // Type
326 #define B_PCH_LPSS_HSUART_STSCMD_BME BIT2 // Bus Master Enable
[all...] |
| /device/linaro/bootloader/edk2/IntelFspPkg/Library/BaseCacheLib/ |
| CacheLibInternal.h | 36 #define B_EFI_MSR_CACHE_MEMORY_TYPE (BIT2 | BIT1 | BIT0)
53 #define B_EFI_MSR_IA32_MTRR_CAP_VARIABLE_SUPPORT (BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0)
|
| /device/linaro/bootloader/edk2/ArmPlatformPkg/Include/Drivers/ |
| HdLcd.h | 55 #define HDLCD_SYNC BIT2 /* Vertical sync */
65 #define HDLCD_BURST_4 BIT2
72 #define HDLCD_DATEN_HIGH BIT2
|
| SP804Timer.h | 35 #define SP804_TIMER_CTRL_PRESCALE_MASK (BIT3|BIT2)
37 #define SP804_PRESCALE_DIV_16 BIT2
|
| /external/llvm/test/Transforms/MemCpyOpt/ |
| 2011-06-02-CallSlotOverwritten.ll | 26 %bit2 = bitcast %struct2* %y to i64*
28 store i64 %load, i64* %bit2, align 8
31 ; CHECK: store i64 %load, i64* %bit2, align 8
|
| /device/linaro/bootloader/edk2/OvmfPkg/Include/IndustryStandard/ |
| Q35MchIch9.h | 46 #define MCH_ESMRAMC_TSEG_8MB BIT2
49 #define MCH_ESMRAMC_TSEG_MASK (BIT2 | BIT1)
|
| /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/ |
| general_definitions.h | 19 #undef BIT2
55 #define BIT2 0x00000004U
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/PlatformDxe/ |
| ExI.c | 99 MmioOr32 ((UINTN) (GetPmcBase() + R_PCH_PMC_MTPMC1), (UINT32) BIT0+BIT1+BIT2);
101 MmioAnd32 ((UINTN) (GetPmcBase() + R_PCH_PMC_MTPMC1), ~((UINT32) BIT0+BIT1+BIT2)); //clear bit 0,1,2
|
| /device/linaro/bootloader/edk2/EmbeddedPkg/Drivers/Lan9118Dxe/ |
| Lan9118DxeUtil.h | 106 #define SOFT_RESET_SELF_TEST BIT2
118 #define PHY_SOFT_RESET_CLEAR_INT BIT2
168 #define STOP_TX_CLEAR BIT2
190 #define START_TX_CLEAR BIT2
241 #define ALLOC_USE_DMA BIT2
|
| /device/linaro/bootloader/edk2/IntelFrameworkModulePkg/Bus/Isa/IsaFloppyPei/ |
| Fdc.h | 35 #define RESET_FDC BIT2 // Reset FDC
101 #define STS0_HA BIT2 // Head Address: the current head address
119 #define STS1_ND BIT2 // No data
133 // BIT2 is unused
151 #define STS3_HD BIT2 // Head Address
|
