1 //==- HexagonSystemInst.td - System Instructions for Hexagon -*- tablegen -*-==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the Hexagon instructions in TableGen format. 11 // 12 //===----------------------------------------------------------------------===// 13 14 //===----------------------------------------------------------------------===// 15 // Cache manipulation instructions. 16 //===----------------------------------------------------------------------===// 17 let mayStore = 1 in 18 class ST_MISC_CACHEOP<dag outs, dag ins, 19 string asmstr, list<dag> pattern = [], 20 bits<3> amode, bits<3> type, bits<1> un> 21 : ST0Inst<outs, ins, asmstr, pattern, "", ST_tc_ld_SLOT0> { 22 23 bits<5> Rs; 24 bits<5> Rt; 25 bits<5> Rd; 26 let Inst{31-28} = 0b1010; 27 let Inst{27-25} = amode; 28 let Inst{24-22} = type; 29 let Inst{21} = un; 30 let Inst{20-16} = Rs; 31 let Inst{12-8} = Rt; 32 let Inst{4-0} = Rd; 33 } 34 35 let mayStore = 1 in 36 class ST_MISC_CACHEOP_SYS<dag outs, dag ins, 37 string asmstr, list<dag> pattern = [], 38 bits<3> amode, bits<3> type, bits<1> un> 39 : SYSInst<outs, ins, asmstr, pattern, ""> { 40 41 bits<5> Rs; 42 bits<5> Rt; 43 bits<5> Rd; 44 let Inst{31-28} = 0b1010; 45 let Inst{27-25} = amode; 46 let Inst{24-22} = type; 47 let Inst{21} = un; 48 let Inst{20-16} = Rs; 49 let Inst{12-8} = Rt; 50 let Inst{4-0} = Rd; 51 } 52 53 54 let isSolo = 1, Rs = 0, Rt = 0, Rd = 0 in { 55 def Y2_syncht: ST_MISC_CACHEOP <(outs), (ins), 56 "syncht" , [], 0b100, 0b001, 0b0>; 57 } 58 59 let Rt = 0, Rd = 0 in { 60 let isSoloAin1 = 1 in { 61 def Y2_dccleana: ST_MISC_CACHEOP <(outs), (ins IntRegs:$Rs), 62 "dccleana($Rs)", [], 0b000, 0b000, 0b0>; 63 def Y2_dcinva: ST_MISC_CACHEOP <(outs), (ins IntRegs:$Rs), 64 "dcinva($Rs)", [], 0b000, 0b000, 0b1>; 65 def Y2_dccleaninva: ST_MISC_CACHEOP <(outs), (ins IntRegs:$Rs), 66 "dccleaninva($Rs)", [], 0b000, 0b001, 0b0>; 67 } 68 } 69 70 let isSoloAX = 1, hasSideEffects = 1, Rd = 0 in { 71 def Y4_l2fetch: ST_MISC_CACHEOP_SYS<(outs), (ins IntRegs:$Rs, IntRegs:$Rt), 72 "l2fetch($Rs, $Rt)", [], 0b011, 0b000, 0b0>; 73 def Y5_l2fetch: ST_MISC_CACHEOP_SYS<(outs), (ins IntRegs:$Rs, DoubleRegs:$Rt), 74 "l2fetch($Rs, $Rt)", [], 0b011, 0b010, 0b0>; 75 } 76 77 let hasSideEffects = 0, isSolo = 1 in 78 class Y2_INVALIDATE_CACHE<string mnemonic, bit MajOp> 79 : JRInst < 80 (outs), (ins IntRegs:$Rs), 81 #mnemonic#"($Rs)" > { 82 bits<5> Rs; 83 84 let IClass = 0b0101; 85 let Inst{27-21} = 0b0110110; 86 let Inst{20-16} = Rs; 87 let Inst{13-12} = 0b00; 88 let Inst{11} = MajOp; 89 } 90 // Instruction cache invalidate 91 def Y2_icinva : Y2_INVALIDATE_CACHE<"icinva", 0b0>; 92 93 // Zero an aligned 32-byte cacheline. 94 let isSoloAin1 = 1 in 95 def Y2_dczeroa: ST0Inst <(outs), (ins IntRegs:$Rs), 96 "dczeroa($Rs)"> { 97 bits<5> Rs; 98 let IClass = 0b1010; 99 let Inst{27-21} = 0b0000110; 100 let Inst{13} = 0b0; 101 let Inst{20-16} = Rs; 102 } 103 104 // Memory synchronization. 105 let hasSideEffects = 0, isSolo = 1 in 106 def Y2_isync: JRInst <(outs), (ins), 107 "isync"> { 108 let IClass = 0b0101; 109 let Inst{27-16} = 0b011111000000; 110 let Inst{13} = 0b0; 111 let Inst{9-0} = 0b0000000010; 112 } 113 114 //===----------------------------------------------------------------------===// 115 // System/User instructions. 116 //===----------------------------------------------------------------------===// 117 // traps and pause 118 let hasSideEffects = 0, isSolo = 1 in 119 class J2_MISC_TRAP_PAUSE<string mnemonic, bits<2> MajOp> 120 : JRInst 121 <(outs), (ins u8Imm:$u8), 122 #mnemonic#"(#$u8)"> { 123 bits<8> u8; 124 125 let IClass = 0b0101; 126 let Inst{27-24} = 0b0100; 127 let Inst{23-22} = MajOp; 128 let Inst{12-8} = u8{7-3}; 129 let Inst{4-2} = u8{2-0}; 130 } 131 def J2_trap0 : J2_MISC_TRAP_PAUSE<"trap0", 0b00>; 132 def J2_trap1 : J2_MISC_TRAP_PAUSE<"trap1", 0b10>; 133 def J2_pause : J2_MISC_TRAP_PAUSE<"pause", 0b01>; 134 135
