Lines Matching defs:in
5 * you may not use this file except in compliance with the License.
10 * Unless required by applicable law or agreed to in writing, software
94 // intrinsic) in an intrinsified call. This will copy the arguments
97 // Note: The actual parameters are required to be in the locations
125 DCHECK(out.IsRegister()); // TODO: Replace this when we support output in memory.
162 FRegister in = locations->InAt(0).AsFpuRegister<FRegister>();
168 __ Mfc1(out_lo, in);
169 __ MoveFromFpuHigh(out_hi, in);
173 __ Mfc1(out, in);
213 Register in = locations->InAt(0).AsRegister<Register>();
215 __ Mtc1(in, out);
259 Register in = locations->InAt(0).AsRegister<Register>();
263 __ Wsbh(out, in);
266 __ Sll(TMP, in, 24);
268 __ Sll(out, in, 16);
273 Register in = locations->InAt(0).AsRegister<Register>();
277 __ Rotr(out, in, 16);
281 // __ Rotr(out, in, 16);
282 __ Sll(TMP, in, 16);
283 __ Srl(out, in, 16);
336 __ Or(TMP, TMP, AT); // Hold in TMP until it's safe
463 Register in = locations->InAt(0).AsRegister<Register>();
466 __ ClzR6(out, in);
468 __ ClzR2(out, in);
497 Register in;
504 // If in_lo is zero then count the number of trailing zeroes in in_hi;
505 // otherwise count the number of trailing zeroes in in_lo.
516 in = out;
518 in = locations->InAt(0).AsRegister<Register>();
520 // Since we only get here in the 32-bit case, this value will never
522 in_lo = in;
529 __ Rotr(out, in, 16);
536 __ Addiu(TMP, in, -1);
537 __ Xor(out, TMP, in);
548 // If in_lo is zero, then we counted the number of trailing zeroes in in_hi so we must add the
549 // number of trailing zeroes in in_lo (32) to get the correct final count
632 // machine instructions each for the values being used in this algorithm).
638 // algorithm the count for a 64-bit operand can be performed in 29
643 Register in = locations->InAt(0).AsRegister<Register>();
645 __ Srl(TMP, in, 1);
648 __ Subu(TMP, in, TMP);
753 FRegister in = locations->InAt(0).AsFpuRegister<FRegister>();
765 // changed when doing abs(NaN). Because of that, we clear sign bit in a different way.
768 __ AbsD(out, in);
770 __ AbsS(out, in);
774 if (in != out) {
775 __ MovD(out, in);
777 __ MoveFromFpuHigh(TMP, in);
787 __ Mfc1(TMP, in);
825 // The comments in this section show the analogous operations which would
826 // be performed if we had 64-bit registers "in", and "out".
827 // __ Dsra32(AT, in, 31);
829 // __ Xor(out, in, AT);
837 Register in = locations->InAt(0).AsRegister<Register>();
840 __ Sra(AT, in, 31);
841 __ Xor(out, in, AT);
1118 // first input register is needed to make sure that value in the
1120 // computing the output value. The logic in the corresponding else
1122 // register isn't clobbered in the event that it's the same register
1326 FRegister in = locations->InAt(0).AsFpuRegister<FRegister>();
1329 __ SqrtD(out, in);
1359 // unaligned halfwords so the code loads individual bytes, in case
1452 // unaligned halfwords so the code stores individual bytes, in case
1539 // path in InstructionCodeGeneratorMIPS::GenerateReferenceLoadWithBakerReadBarrier.
1725 // The "offset" argument is passed as a "long", i.e., it's 64-bits in
1901 // Temporary register used in CAS by (Baker) read barrier.
1937 // Need to make sure the reference stored in the field is a to-space
1986 // in the case that the store fails. Whether the
1991 // of those two types. It's left here in case the code needs to support
1992 // other types in the future.
2152 // Assertions that must hold in order to compare strings 4 bytes at a time.
2182 // If loop does not result in returning false, we return true.
2222 // fits in a valid 16-bit (MIPS halfword) value. If it doesn't then
2223 // the character being searched for, if it exists in the string, is
2224 // encoded using UTF-16 and stored in the string as two (16-bit)
2374 FRegister in = locations->InAt(0).AsFpuRegister<FRegister>();
2381 __ ClassD(FTMP, in);
2383 __ ClassS(FTMP, in);
2391 __ MoveFromFpuHigh(TMP, in);
2394 __ Mfc1(TMP, in);
2402 __ Mfc1(AT, in);
2461 Register in = locations->InAt(0).AsRegister<Register>();
2465 __ ClzR6(TMP, in);
2467 __ ClzR2(TMP, in);
2470 __ Srlv(AT, AT, TMP); // Srlv shifts in the range of [0;31] bits (lower 5 bits of arg).
2471 __ And(out, AT, in); // So this is required for 0 (=shift by 32).
2515 Register in = locations->InAt(0).AsRegister<Register>();
2518 __ Subu(TMP, ZERO, in);
2519 __ And(out, TMP, in);
2554 FRegister in = locations->InAt(0).AsFpuRegister<FRegister>();
2561 // out = floor(in);
2564 // TMP = ((in - out) >= 0.5) ? 1 : 0;
2569 // out = floor(in);
2570 __ FloorWS(FTMP, in);
2583 // TMP = (0.5f <= (in - out)) ? -1 : 0;
2586 __ SubS(FTMP, in, FTMP);
2595 // if (in.isNaN) {
2599 // out = floor.w.s(in);
2604 // * too large to fit in a 32-bit integer.
2607 // TMP = (in < 0.0f) ? 1 : 0;
2619 // TMP = ((in - out) >= 0.5f) ? 1 : 0;
2626 __ CunS(in, in);
2632 // out = floor(in);
2633 __ FloorWS(FTMP, in);
2643 __ ColtS(in, FTMP);
2649 // TMP = (0.5f <= (in - out)) ? -1 : 0;
2652 __ SubS(FTMP, in, FTMP);
2686 // Check assumption that sizeof(Char) is 2 (used in scaling below).
2704 // Location of data in char array buffer.
2781 FRegister in = locations->InAt(0).AsFpuRegister<FRegister>();
2782 DCHECK_EQ(in, F12);
3022 // Where is the length in the Array?
3096 // We have already checked in the LocationsBuilder for the constant case.
3112 // Check assumption that sizeof(Char) is 2 (used in scaling below).
3171 // Just embed the j.l.Integer in the code.
3179 // TODO: If we JIT, we could allocate the j.l.Integer now, and store it in the
3192 Register in = locations->InAt(0).AsRegister<Register>();
3196 // Is (info.low <= in) && (in <= info.high)?
3197 __ Addiu32(out, in, -info.low);
3206 // This means that "in" is outside of the range [info.low, info.high].
3224 __ StoreToOffset(kStoreWord, in, out, info.value_offset);
