Lines Matching defs:out
123 Location out = invoke_->GetLocations()->Out();
124 if (out.IsValid()) {
125 DCHECK(out.IsRegister()); // TODO: Replace this when we support output in memory.
126 DCHECK(!invoke_->GetLocations()->GetLiveRegisters()->ContainsCoreRegister(out.reg()));
127 MoveFromReturnRegister(out, invoke_->GetType(), codegen);
165 Register out_lo = locations->Out().AsRegisterPairLow<Register>();
166 Register out_hi = locations->Out().AsRegisterPairHigh<Register>();
171 Register out = locations->Out().AsRegister<Register>();
173 __ Mfc1(out, in);
204 FRegister out = locations->Out().AsFpuRegister<FRegister>();
210 __ Mtc1(in_lo, out);
211 __ MoveToFpuHigh(in_hi, out);
215 __ Mtc1(in, out);
260 Register out = locations->Out().AsRegister<Register>();
263 __ Wsbh(out, in);
264 __ Seh(out, out);
268 __ Sll(out, in, 16);
269 __ Srl(out, out, 24);
270 __ Or(out, out, TMP);
274 Register out = locations->Out().AsRegister<Register>();
277 __ Rotr(out, in, 16);
278 __ Wsbh(out, out);
281 // __ Rotr(out, in, 16);
283 __ Srl(out, in, 16);
284 __ Or(out, out, TMP);
285 // __ Wsbh(out, out);
287 __ And(TMP, out, AT);
289 __ Srl(out, out, 8);
290 __ And(out, out, AT);
291 __ Or(out, out, TMP);
295 __ Bitswap(out, out);
298 __ And(TMP, out, AT);
300 __ Srl(out, out, 4);
301 __ And(out, out, AT);
302 __ Or(out, TMP, out);
304 __ And(TMP, out, AT);
306 __ Srl(out, out, 2);
307 __ And(out, out, AT);
308 __ Or(out, TMP, out);
310 __ And(TMP, out, AT);
312 __ Srl(out, out, 1);
313 __ And(out, out, AT);
314 __ Or(out, TMP, out);
320 Register out_lo = locations->Out().AsRegisterPairLow<Register>();
321 Register out_hi = locations->Out().AsRegisterPairHigh<Register>();
447 Register out = locations->Out().AsRegister<Register>();
461 __ Addu(out, AT, TMP);
466 __ ClzR6(out, in);
468 __ ClzR2(out, in);
495 Register out = locations->Out().AsRegister<Register>();
506 // out = in_lo ? in_lo : in_hi;
508 __ Seleqz(out, in_hi, in_lo);
510 __ Or(out, out, TMP);
512 __ Movz(out, in_hi, in_lo);
513 __ Movn(out, in_lo, in_lo);
516 in = out;
529 __ Rotr(out, in, 16);
530 __ Wsbh(out, out);
531 __ Bitswap(out, out);
532 __ ClzR6(out, out);
537 __ Xor(out, TMP, in);
538 __ And(out, out, TMP);
540 __ ClzR2(out, out);
544 __ Subu(out, TMP, out);
556 __ Addu(out, out, TMP);
618 Register out = locations->Out().AsRegister<Register>();
650 __ And(out, TMP, AT);
653 __ Addu(TMP, out, TMP);
654 __ Srl(out, TMP, 4);
655 __ Addu(out, out, TMP);
657 __ And(out, out, AT);
660 __ MulR6(out, out, TMP);
662 __ MulR2(out, out, TMP);
664 __ Srl(out, out, 24);
672 Register out_lo = out;
707 __ Srl(out, TMP, 4);
708 __ And(out, out, AT);
710 __ Addu(out, out, TMP);
715 __ MulR6(out, out, AT);
717 __ MulR2(out, out, AT);
720 __ Srl(out, out, 24);
754 FRegister out = locations->Out().AsFpuRegister<FRegister>();
768 __ AbsD(out, in);
770 __ AbsS(out, in);
774 if (in != out) {
775 __ MovD(out, in);
785 __ MoveToFpuHigh(TMP, out);
795 __ Mtc1(TMP, out);
822 Register out_lo = locations->Out().AsRegisterPairLow<Register>();
823 Register out_hi = locations->Out().AsRegisterPairHigh<Register>();
826 // be performed if we had 64-bit registers "in", and "out".
829 // __ Xor(out, in, AT);
832 // __ Dsubu(out, out, AT);
838 Register out = locations->Out().AsRegister<Register>();
841 __ Xor(out, in, AT);
842 __ Subu(out, out, AT);
869 FRegister out = locations->Out().AsFpuRegister<FRegister>();
876 FRegister ftmp = ((out != a) && (out != b)) ? out : FTMP;
894 if (ftmp != out) {
895 __ MovD(out, ftmp);
903 __ MinD(out, a, b);
905 __ MaxD(out, a, b);
917 if (ftmp != out) {
918 __ MovS(out, ftmp);
926 __ MinS(out, a, b);
928 __ MaxS(out, a, b);
986 __ Mtc1(AT, out);
987 __ MoveToFpuHigh(TMP, out);
989 __ Mtc1(TMP, out);
1016 __ MovtD(out, a);
1017 __ MovfD(out, b);
1019 __ MovtS(out, a);
1020 __ MovfS(out, b);
1131 Register out_lo = locations->Out().AsRegisterPairLow<Register>();
1132 Register out_hi = locations->Out().AsRegisterPairHigh<Register>();
1172 Register out = locations->Out().AsRegister<Register>();
1175 if (out != a) {
1176 __ Move(out, a);
1187 __ Or(out, TMP, AT);
1196 Register out_lo = locations->Out().AsRegisterPairLow<Register>();
1197 Register out_hi = locations->Out().AsRegisterPairHigh<Register>();
1238 Register out = locations->Out().AsRegister<Register>();
1241 if (out != a) {
1242 __ Move(out, a);
1247 if (out != a) {
1248 __ Movn(out, a, AT);
1250 if (out != b) {
1251 __ Movz(out, b, AT);
1254 if (out != a) {
1255 __ Movz(out, a, AT);
1257 if (out != b) {
1258 __ Movn(out, b, AT);
1327 FRegister out = locations->Out().AsFpuRegister<FRegister>();
1329 __ SqrtD(out, in);
1340 Register out = invoke->GetLocations()->Out().AsRegister<Register>();
1342 __ Lb(out, adr, 0);
1353 Register out = invoke->GetLocations()->Out().AsRegister<Register>();
1356 __ Lh(out, adr, 0);
1363 __ Lb(out, adr, 0); // This byte can be either sign-extended, or
1366 __ Ins(out, AT, 8, 24);
1371 __ Lb(out, adr, 1); // This byte must be sign-extended.
1372 __ Sll(out, out, 8);
1373 __ Or(out, out, AT);
1385 Register out = invoke->GetLocations()->Out().AsRegister<Register>();
1388 __ Lw(out, adr, 0);
1390 __ Lwr(out, adr, 0);
1391 __ Lwl(out, adr, 3);
1403 Register out_lo = invoke->GetLocations()->Out().AsRegisterPairLow<Register>();
1404 Register out_hi = invoke->GetLocations()->Out().AsRegisterPairHigh<Register>();
1510 Register out = invoke->GetLocations()->Out().AsRegister<Register>();
1513 out,
1557 Location trg_loc = locations->Out();
1768 bool value_can_be_null = true; // TODO: Worth finding out this information?
1918 Location out_loc = locations->Out();
1919 Register out = out_loc.AsRegister<Register>();
1921 DCHECK_NE(base, out);
1922 DCHECK_NE(offset_lo, out);
1923 DCHECK_NE(expected, out);
1932 bool value_can_be_null = true; // TODO: Worth finding out this information?
1973 __ LlR6(out, TMP);
1975 __ LlR2(out, TMP);
1981 __ Subu(out, out, expected); // If we didn't get the 'expected'
1982 __ Sltiu(out, out, 1); // value, set 'out' to false, and
1983 __ Beqz(out, &exit_loop); // return.
1984 __ Move(out, value); // Use 'out' for the 'store conditional' instruction.
1988 // correct Boolean value into the 'out' register.
1995 __ ScR6(out, TMP);
1997 __ ScR2(out, TMP);
2000 __ Beqz(out, &loop_head); // If we couldn't do the read-modify-write
2091 Register out = locations->Out().AsRegister<Register>();
2115 __ LoadConst32(out, 1);
2172 __ Lw(out, TMP, value_offset);
2174 __ Bne(out, temp2, &return_false);
2184 __ LoadConst32(out, 1);
2189 __ LoadConst32(out, 0);
2375 Register out = locations->Out().AsRegister<Register>();
2385 __ Mfc1(out, FTMP);
2386 __ Andi(out, out, kPositiveInfinity | kNegativeInfinity);
2387 __ Sltu(out, ZERO, out);
2406 __ Sltiu(out, TMP, 1);
2437 Register out_lo = locations->Out().AsRegisterPairLow<Register>();
2438 Register out_hi = locations->Out().AsRegisterPairHigh<Register>();
2462 Register out = locations->Out().AsRegister<Register>();
2471 __ And(out, AT, in); // So this is required for 0 (=shift by 32).
2502 Register out_lo = locations->Out().AsRegisterPairLow<Register>();
2503 Register out_hi = locations->Out().AsRegisterPairHigh<Register>();
2516 Register out = locations->Out().AsRegister<Register>();
2519 __ And(out, TMP, in);
2556 Register out = locations->Out().AsRegister<Register>();
2561 // out = floor(in);
2563 // if (out != MAX_VALUE && out != MIN_VALUE) {
2564 // TMP = ((in - out) >= 0.5) ? 1 : 0;
2565 // return out += TMP;
2567 // return out;
2569 // out = floor(in);
2571 __ Mfc1(out, FTMP);
2573 // if (out != MAX_VALUE && out != MIN_VALUE)
2574 __ Addiu(TMP, out, 1);
2575 __ Aui(TMP, TMP, 0x8000); // TMP = out + 0x8000 0001
2576 // or out - 0x7FFF FFFF.
2577 // IOW, TMP = 1 if out = Int.MIN_VALUE
2578 // or TMP = 0 if out = Int.MAX_VALUE.
2579 __ Srl(TMP, TMP, 1); // TMP = 0 if out = Int.MIN_VALUE
2580 // or out = Int.MAX_VALUE.
2583 // TMP = (0.5f <= (in - out)) ? -1 : 0;
2592 // Return out -= TMP.
2593 __ Subu(out, out, TMP);
2599 // out = floor.w.s(in);
2606 // if (out == Integer.MAX_VALUE) {
2609 // * If TMP is 1, then adding it to out will wrap its value from
2612 // return out += TMP;
2619 // TMP = ((in - out) >= 0.5f) ? 1 : 0;
2620 // return out += TMP;
2629 __ Move(out, ZERO);
2632 // out = floor(in);
2634 __ Mfc1(out, FTMP);
2638 // TMP = (out = java.lang.Integer.MAX_VALUE) ? -1 : 0;
2640 __ Bne(AT, out, &finite);
2649 // TMP = (0.5f <= (in - out)) ? -1 : 0;
2660 // Return out -= TMP.
2661 __ Subu(out, out, TMP);
2783 FRegister out = locations->Out().AsFpuRegister<FRegister>();
2784 DCHECK_EQ(out, F0);
2797 FRegister out = locations->Out().AsFpuRegister<FRegister>();
2798 DCHECK_EQ(out, F0);
3082 // Bail out if the source and destination are the same (to handle overlap).
3085 // Bail out if the source is null.
3088 // Bail out if the destination is null.
3095 // If the length is negative, bail out.
3111 // Okay, everything checks out. Finally time to do the copy.
3166 Register out = locations->Out().AsRegister<Register>();
3176 __ LoadConst32(out, address);
3186 __ StoreConstToOffset(kStoreWord, value, out, info.value_offset, TMP);
3197 __ Addiu32(out, in, -info.low);
3198 // As unsigned quantities is out < (info.high - info.low + 1)?
3200 __ Sltiu(AT, out, count);
3203 __ Sltu(AT, out, AT);
3205 // Branch if out >= (info.high - info.low + 1).
3213 __ ShiftAndAdd(out, out, TMP, TIMES_4);
3214 __ Lw(out, out, 0);
3215 __ MaybeUnpoisonHeapReference(out);
3224 __ StoreToOffset(kStoreWord, in, out, info.value_offset);
