Lines Matching defs:in
5 * you may not use this file except in compliance with the License.
10 * Unless required by applicable law or agreed to in writing, software
82 // intrinsic) in an intrinsified call. This will copy the arguments
85 // Note: The actual parameters are required to be in the locations
114 DCHECK(out.IsRegister()); // TODO: Replace this when we support output in memory.
151 FpuRegister in = locations->InAt(0).AsFpuRegister<FpuRegister>();
155 __ Dmfc1(out, in);
157 __ Mfc1(out, in);
188 GpuRegister in = locations->InAt(0).AsRegister<GpuRegister>();
192 __ Dmtc1(in, out);
194 __ Mtc1(in, out);
227 GpuRegister in = locations->InAt(0).AsRegister<GpuRegister>();
232 __ Dsbh(out, in);
236 __ Rotr(out, in, 16);
240 __ Dsbh(out, in);
279 GpuRegister in = locations->InAt(0).AsRegister<GpuRegister>();
283 __ Dclz(out, in);
285 __ Clz(out, in);
310 Location in = locations->InAt(0);
314 __ Dsbh(out.AsRegister<GpuRegister>(), in.AsRegister<GpuRegister>());
319 __ Rotr(out.AsRegister<GpuRegister>(), in.AsRegister<GpuRegister>(), 16);
349 GpuRegister in = locations->InAt(0).AsRegister<GpuRegister>();
353 __ Rotr(out, in, 16);
357 __ Dsbh(out, in);
393 GpuRegister in = locations->InAt(0).AsRegister<GpuRegister>();
409 // machine instructions each for the values being used in this algorithm).
412 // For a 64-bit operand this can be performed in 24 instructions compared
415 // There are algorithms which are faster in the cases where very few
421 __ Srl(TMP, in, 1);
424 __ Subu(TMP, in, TMP);
438 __ Dsrl(TMP, in, 1);
441 __ Dsubu(TMP, in, TMP);
476 FpuRegister in = locations->InAt(0).AsFpuRegister<FpuRegister>();
480 __ AbsD(out, in);
482 __ AbsS(out, in);
513 GpuRegister in = locations->InAt(0).AsRegister<GpuRegister>();
517 __ Dsra32(AT, in, 31);
518 __ Xor(out, in, AT);
521 __ Sra(AT, in, 31);
522 __ Xor(out, in, AT);
686 // first input register is needed to make sure that value in the
688 // computing the output value. The logic in the corresponding else
690 // register isn't clobbered in the event that it's the same register
770 FpuRegister in = locations->InAt(0).AsFpuRegister<FpuRegister>();
773 __ SqrtD(out, in);
794 FpuRegister in = locations->InAt(0).AsFpuRegister<FpuRegister>();
797 __ RintD(out, in);
820 FpuRegister in = locations->InAt(0).AsFpuRegister<FpuRegister>();
823 DCHECK_NE(in, out);
827 // double floor/ceil(double in) {
828 // if in.isNaN || in.isInfinite || in.isZero {
829 // return in;
831 __ ClassD(out, in);
834 __ MovD(out, in);
837 // Long outLong = floor/ceil(in);
842 // // be returned in these cases.
843 // // There is also a small probability that floor(in)/ceil(in)
845 // // Long.MAX_VALUE or Long.MIN_VALUE. In these cases, this
847 // return in;
850 __ FloorLD(out, in);
852 __ CeilLD(out, in);
855 __ MovD(out, in);
887 FpuRegister in = locations->InAt(0).AsFpuRegister<FpuRegister>();
895 // out = floor(in);
898 // TMP = ((in - out) >= 0.5) ? 1 : 0;
903 // out = floor(in);
905 __ FloorLD(FTMP, in);
908 __ FloorWS(FTMP, in);
933 // TMP = (0.5 <= (in - out)) ? -1 : 0;
937 __ SubD(FTMP, in, FTMP);
944 __ SubS(FTMP, in, FTMP);
1139 // path in InstructionCodeGeneratorMIPS64::GenerateReferenceLoadWithBakerReadBarrier.
1473 // Temporary register used in CAS by (Baker) read barrier.
1508 // Need to make sure the reference stored in the field is a to-space
1559 // in the case that the store fails. Whether the
1730 // Assertions that must hold in order to compare strings 8 bytes at a time.
1754 // If loop does not result in returning false, we return true.
1934 FpuRegister in = locations->InAt(0).AsFpuRegister<FpuRegister>();
1938 __ ClassD(FTMP, in);
1940 __ ClassS(FTMP, in);
1985 // Check assumption that sizeof(Char) is 2 (used in scaling below).
2003 // Location of data in char array buffer.
2123 // Where is the length in the Array?
2197 // We have already checked in the LocationsBuilder for the constant case.
2213 // Check assumption that sizeof(Char) is 2 (used in scaling below).
2255 GpuRegister in = locations->InAt(0).AsRegister<GpuRegister>();
2259 __ Dclz(TMP, in);
2263 __ Clz(TMP, in);
2267 // For either value of "type", when "in" is zero, "out" should also
2268 // be zero. Without this extra "and" operation, when "in" is zero,
2273 __ And(out, AT, in);
2299 GpuRegister in = locations->InAt(0).AsRegister<GpuRegister>();
2303 __ Dsubu(TMP, ZERO, in);
2305 __ Subu(TMP, ZERO, in);
2307 __ And(out, TMP, in);
2353 FpuRegister in = locations->InAt(0).AsFpuRegister<FpuRegister>();
2354 DCHECK_EQ(in, F12);
2550 // Just embed the j.l.Integer in the code.
2558 // TODO: If we JIT, we could allocate the j.l.Integer now, and store it in the
2571 GpuRegister in = locations->InAt(0).AsRegister<GpuRegister>();
2575 // Is (info.low <= in) && (in <= info.high)?
2576 __ Addiu32(out, in, -info.low);
2580 // This means that "in" is outside of the range [info.low, info.high].
2598 __ StoreToOffset(kStoreWord, in, out, info.value_offset);
