Lines Matching defs:out
112 Location out = invoke_->GetLocations()->Out();
113 if (out.IsValid()) {
114 DCHECK(out.IsRegister()); // TODO: Replace this when we support output in memory.
115 DCHECK(!invoke_->GetLocations()->GetLiveRegisters()->ContainsCoreRegister(out.reg()));
116 MoveFromReturnRegister(out, invoke_->GetType(), codegen);
152 GpuRegister out = locations->Out().AsRegister<GpuRegister>();
155 __ Dmfc1(out, in);
157 __ Mfc1(out, in);
189 FpuRegister out = locations->Out().AsFpuRegister<FpuRegister>();
192 __ Dmtc1(in, out);
194 __ Mtc1(in, out);
228 GpuRegister out = locations->Out().AsRegister<GpuRegister>();
232 __ Dsbh(out, in);
233 __ Seh(out, out);
236 __ Rotr(out, in, 16);
237 __ Wsbh(out, out);
240 __ Dsbh(out, in);
241 __ Dshd(out, out);
280 GpuRegister out = locations->Out().AsRegister<GpuRegister>();
283 __ Dclz(out, in);
285 __ Clz(out, in);
311 Location out = locations->Out();
314 __ Dsbh(out.AsRegister<GpuRegister>(), in.AsRegister<GpuRegister>());
315 __ Dshd(out.AsRegister<GpuRegister>(), out.AsRegister<GpuRegister>());
316 __ Dbitswap(out.AsRegister<GpuRegister>(), out.AsRegister<GpuRegister>());
317 __ Dclz(out.AsRegister<GpuRegister>(), out.AsRegister<GpuRegister>());
319 __ Rotr(out.AsRegister<GpuRegister>(), in.AsRegister<GpuRegister>(), 16);
320 __ Wsbh(out.AsRegister<GpuRegister>(), out.AsRegister<GpuRegister>());
321 __ Bitswap(out.AsRegister<GpuRegister>(), out.AsRegister<GpuRegister>());
322 __ Clz(out.AsRegister<GpuRegister>(), out.AsRegister<GpuRegister>());
350 GpuRegister out = locations->Out().AsRegister<GpuRegister>();
353 __ Rotr(out, in, 16);
354 __ Wsbh(out, out);
355 __ Bitswap(out, out);
357 __ Dsbh(out, in);
358 __ Dshd(out, out);
359 __ Dbitswap(out, out);
392 GpuRegister out = locations->Out().AsRegister<GpuRegister>();
426 __ And(out, TMP, AT);
429 __ Addu(TMP, out, TMP);
430 __ Srl(out, TMP, 4);
431 __ Addu(out, out, TMP);
433 __ And(out, out, AT);
435 __ MulR6(out, out, TMP);
436 __ Srl(out, out, 24);
443 __ And(out, TMP, AT);
446 __ Daddu(TMP, out, TMP);
447 __ Dsrl(out, TMP, 4);
448 __ Daddu(out, out, TMP);
450 __ And(outout, AT);
452 __ Dmul(out, out, TMP);
453 __ Dsrl32(out, out, 24);
477 FpuRegister out = locations->Out().AsFpuRegister<FpuRegister>();
480 __ AbsD(out, in);
482 __ AbsS(out, in);
514 GpuRegister out = locations->Out().AsRegister<GpuRegister>();
518 __ Xor(out, in, AT);
519 __ Dsubu(out, out, AT);
522 __ Xor(out, in, AT);
523 __ Subu(out, out, AT);
551 FpuRegister out = locations->Out().AsFpuRegister<FpuRegister>();
555 FpuRegister ftmp = ((out != a) && (out != b)) ? out : FTMP;
573 if (ftmp != out) {
574 __ MovD(out, ftmp);
582 __ MinD(out, a, b);
584 __ MaxD(out, a, b);
596 if (ftmp != out) {
597 __ MovS(out, ftmp);
605 __ MinS(out, a, b);
607 __ MaxS(out, a, b);
664 GpuRegister out = locations->Out().AsRegister<GpuRegister>();
667 if (out != lhs) {
668 __ Move(out, lhs);
694 if (out == lhs) {
697 __ Seleqz(out, lhs, AT);
700 __ Selnez(out, lhs, AT);
706 __ Seleqz(out, rhs, AT);
709 __ Selnez(out, rhs, AT);
713 __ Or(out, out, AT);
771 FpuRegister out = locations->Out().AsFpuRegister<FpuRegister>();
773 __ SqrtD(out, in);
795 FpuRegister out = locations->Out().AsFpuRegister<FpuRegister>();
797 __ RintD(out, in);
821 FpuRegister out = locations->Out().AsFpuRegister<FpuRegister>();
823 DCHECK_NE(in, out);
831 __ ClassD(out, in);
832 __ Dmfc1(AT, out);
834 __ MovD(out, in);
850 __ FloorLD(out, in);
852 __ CeilLD(out, in);
854 __ Dmfc1(AT, out);
855 __ MovD(out, in);
865 // double out = outLong;
866 // return out;
867 __ Dmtc1(AT, out);
868 __ Cvtdl(out, out);
889 GpuRegister out = locations->Out().AsRegister<GpuRegister>();
895 // out = floor(in);
897 // if (out != MAX_VALUE && out != MIN_VALUE) {
898 // TMP = ((in - out) >= 0.5) ? 1 : 0;
899 // return out += TMP;
901 // return out;
903 // out = floor(in);
906 __ Dmfc1(out, FTMP);
909 __ Mfc1(out, FTMP);
912 // if (out != MAX_VALUE && out != MIN_VALUE)
914 __ Daddiu(TMP, out, 1);
915 out + 0x8000 0000 0000 0001
916 // or out - 0x7FFF FFFF FFFF FFFF.
917 // IOW, TMP = 1 if out = Long.MIN_VALUE
918 // or TMP = 0 if out = Long.MAX_VALUE.
919 __ Dsrl(TMP, TMP, 1); // TMP = 0 if out = Long.MIN_VALUE
920 // or out = Long.MAX_VALUE.
923 __ Addiu(TMP, out, 1);
924 __ Aui(TMP, TMP, 0x8000); // TMP = out + 0x8000 0001
925 // or out - 0x7FFF FFFF.
926 // IOW, TMP = 1 if out = Int.MIN_VALUE
927 // or TMP = 0 if out = Int.MAX_VALUE.
928 __ Srl(TMP, TMP, 1); // TMP = 0 if out = Int.MIN_VALUE
929 // or out = Int.MAX_VALUE.
933 // TMP = (0.5 <= (in - out)) ? -1 : 0;
950 // Return out -= TMP.
952 __ Dsubu(out, out, TMP);
954 __ Subu(out, out, TMP);
996 GpuRegister out = invoke->GetLocations()->Out().AsRegister<GpuRegister>();
998 __ Lb(out, adr, 0);
1009 GpuRegister out = invoke->GetLocations()->Out().AsRegister<GpuRegister>();
1011 __ Lh(out, adr, 0);
1022 GpuRegister out = invoke->GetLocations()->Out().AsRegister<GpuRegister>();
1024 __ Lw(out, adr, 0);
1035 GpuRegister out = invoke->GetLocations()->Out().AsRegister<GpuRegister>();
1037 __ Ld(out, adr, 0);
1110 GpuRegister out = invoke->GetLocations()->Out().AsRegister<GpuRegister>();
1113 out,
1156 Location trg_loc = locations->Out();
1335 bool value_can_be_null = true; // TODO: Worth finding out this information?
1489 Location out_loc = locations->Out();
1490 GpuRegister out = out_loc.AsRegister<GpuRegister>();
1492 DCHECK_NE(base, out);
1493 DCHECK_NE(offset, out);
1494 DCHECK_NE(expected, out);
1503 bool value_can_be_null = true; // TODO: Worth finding out this information?
1543 __ Lld(out, TMP);
1547 __ Ll(out, TMP);
1550 // 32-bit references must be zero-extended. Zero-extend `out`.
1551 __ Dext(out, out, 0, 32);
1554 __ Dsubu(out, out, expected); // If we didn't get the 'expected'
1555 __ Sltiu(out, out, 1); // value, set 'out' to false, and
1556 __ Beqzc(out, &exit_loop); // return.
1557 __ Move(out, value); // Use 'out' for the 'store conditional' instruction.
1561 // correct Boolean value into the 'out' register.
1563 __ Scd(out, TMP);
1565 __ Sc(out, TMP);
1567 __ Beqzc(out, &loop_head); // If we couldn't do the read-modify-write
1668 GpuRegister out = locations->Out().AsRegister<GpuRegister>();
1692 __ LoadConst64(out, 1);
1744 __ Ld(out, TMP, value_offset);
1746 __ Bnec(out, temp2, &return_false);
1756 __ LoadConst64(out, 1);
1761 __ LoadConst64(out, 0);
1935 GpuRegister out = locations->Out().AsRegister<GpuRegister>();
1942 __ Mfc1(out, FTMP);
1943 __ Andi(out, out, kPositiveInfinity | kNegativeInfinity);
1944 __ Sltu(out, ZERO, out);
2183 // Bail out if the source and destination are the same (to handle overlap).
2186 // Bail out if the source is null.
2189 // Bail out if the destination is null.
2196 // If the length is negative, bail out.
2212 // Okay, everything checks out. Finally time to do the copy.
2256 GpuRegister out = locations->Out().AsRegister<GpuRegister>();
2267 // For either value of "type", when "in" is zero, "out" should also
2269 // "out" would be either Integer.MIN_VALUE, or Long.MIN_VALUE because
2273 __ And(out, AT, in);
2300 GpuRegister out = locations->Out().AsRegister<GpuRegister>();
2307 __ And(out, TMP, in);
2355 FpuRegister out = locations->Out().AsFpuRegister<FpuRegister>();
2356 DCHECK_EQ(out, F0);
2369 FpuRegister out = locations->Out().AsFpuRegister<FpuRegister>();
2370 DCHECK_EQ(out, F0);
2545 GpuRegister out = locations->Out().AsRegister<GpuRegister>();
2555 __ LoadConst64(out, address);
2565 __ StoreConstToOffset(kStoreWord, value, out, info.value_offset, TMP);
2576 __ Addiu32(out, in, -info.low);
2577 // As unsigned quantities is out < (info.high - info.low + 1)?
2579 // Branch if out >= (info.high - info.low + 1).
2581 __ Bgeuc(out, AT, &allocate);
2587 __ Dlsa(out, out, TMP, TIMES_4);
2588 __ Lwu(out, out, 0);
2589 __ MaybeUnpoisonHeapReference(out);
2598 __ StoreToOffset(kStoreWord, in, out, info.value_offset);
