Lines Matching defs:out
148 Location output = locations->Out();
154 Location output = locations->Out();
197 CpuRegister out = locations->Out().AsRegister<CpuRegister>();
202 __ bswapl(out);
203 __ sarl(out, Immediate(16));
206 __ bswapl(out);
209 __ bswapq(out);
259 Location output = locations->Out();
302 Location output = locations->Out();
303 CpuRegister out = output.AsRegister<CpuRegister>();
308 __ movq(mask, out);
311 __ addq(out, mask);
312 __ xorq(out, mask);
315 __ movl(mask, out);
318 __ addl(out, mask);
319 __ xorl(out, mask);
346 Location out_loc = locations->Out();
347 XmmRegister out = out_loc.AsFpuRegister<XmmRegister>();
355 // (out := op1)
356 // out <=? op2
358 // if out is min jmp done
363 // out := NaN
365 // out := op2
368 // This removes one jmp, but needs to copy one input (op1) to out.
370 // TODO: This is straight from Quick. Make NaN an out-of-line slowpath?
376 __ ucomisd(out, op2);
378 __ ucomiss(out, op2);
389 __ orpd(out, op2);
391 __ orps(out, op2);
395 __ andpd(out, op2);
397 __ andps(out, op2);
405 __ movsd(out, codegen->LiteralInt64Address(INT64_C(0x7FF8000000000000)));
407 __ movss(out, codegen->LiteralInt32Address(INT32_C(0x7FC00000)));
411 // out := op2;
414 __ movsd(out, op2);
416 __ movss(out, op2);
480 DCHECK(locations->Out().Equals(op1_loc));
484 CpuRegister out = locations->Out().AsRegister<CpuRegister>();
487 // (out := op1)
488 // out <=? op2
489 // if out is min jmp done
490 // out := op2
494 __ cmpq(out, op2);
496 __ cmpl(out, op2);
499 __ cmov(is_min ? Condition::kGreater : Condition::kLess, out, op2, is_long);
558 XmmRegister out = locations->Out().AsFpuRegister<XmmRegister>();
560 GetAssembler()->sqrtsd(out, in);
571 Location out = invoke->GetLocations()->Out();
572 if (out.IsValid()) {
573 DCHECK(out.IsRegister());
574 codegen->MoveFromReturnRegister(out, invoke->GetType());
606 XmmRegister out = locations->Out().AsFpuRegister<XmmRegister>();
607 __ roundsd(out, in, Immediate(round_mode));
672 CpuRegister out = locations->Out().AsRegister<CpuRegister>();
694 codegen_->Load32BitValue(out, kPrimIntMax);
695 __ cvtsi2ss(t2, out);
697 __ j(kAboveEqual, &done); // clipped to max (already in out), does not jump on unordered
698 __ movl(out, Immediate(0)); // does not change flags
699 __ j(kUnordered, &done); // NaN mapped to 0 (just moved in out)
700 __ cvttss2si(out, t1);
716 CpuRegister out = locations->Out().AsRegister<CpuRegister>();
738 codegen_->Load64BitValue(out, kPrimLongMax);
739 __ cvtsi2sd(t2, out, /* is64bit */ true);
741 __ j(kAboveEqual, &done); // clipped to max (already in out), does not jump on unordered
742 __ movl(out, Immediate(0)); // does not change flags, implicit zero extension to 64-bit
743 __ j(kUnordered, &done); // NaN mapped to 0 (just moved in out)
744 __ cvttsd2si(out, t1, /* is64bit */ true);
929 // Check to see if we have known failures that will cause us to have to bail out
1052 // Bail out if the source and destination are the same.
1056 // Bail out if the source is null.
1060 // Bail out if the destination is null.
1064 // If the length is negative, bail out.
1084 // Okay, everything checks out. Finally time to do the copy.
1236 // Bail out if the source is null.
1242 // Bail out if the destination is null.
1247 // If the length is negative, bail out.
1312 // Bail out if the destination is not a non primitive array.
1333 // Bail out if the source is not a non primitive array.
1387 // Bail out if the source is not a non primitive array.
1558 CpuRegister rsi = locations->Out().AsRegister<CpuRegister>();
1684 CpuRegister out = locations->Out().AsRegister<CpuRegister>();
1690 DCHECK_EQ(out.AsRegister(), RDI);
1733 // Mask out first bit used as compression flag.
1797 __ leal(out, Address(string_length, -1));
1804 __ movl(out, Immediate(-1));
1997 CpuRegister out = locations->Out().AsRegister<CpuRegister>(); // == address, here for clarity.
2002 __ movsxb(out, Address(address, 0));
2005 __ movsxw(out, Address(address, 0));
2008 __ movl(out, Address(address, 0));
2011 __ movq(out, Address(address, 0));
2145 CpuRegister out = invoke->GetLocations()->Out().AsRegister<CpuRegister>();
2146 GetAssembler()->gs()->movl(out, Address::Absolute(Thread::PeerOffset<kX86_64PointerSize>(),
2160 Location output_loc = locations->Out();
2325 bool value_can_be_null = true; // TODO: Worth finding out this information?
2417 Location out_loc = locations->Out();
2418 CpuRegister out = out_loc.AsRegister<CpuRegister>();
2429 bool value_can_be_null = true; // TODO: Worth finding out this information?
2481 __ setcc(kZero, out);
2482 __ movzxb(out, out);
2491 // Ensure `value` is different from `out`, so that unpoisoning
2493 DCHECK_NE(value_reg, out.AsRegister());
2496 // Ensure `expected` is different from `out`, so that unpoisoning
2498 DCHECK_NE(expected.AsRegister(), out.AsRegister());
2514 __ setcc(kZero, out);
2515 __ movzxb(out, out);
2643 CpuRegister out = locations->Out().AsRegister<CpuRegister>();
2651 codegen->Load32BitValue(out, result);
2657 __ popcntq(out, src.AsRegister<CpuRegister>());
2659 __ popcntl(out, src.AsRegister<CpuRegister>());
2663 __ popcntq(out, Address(CpuRegister(RSP), src.GetStackIndex()));
2666 __ popcntl(out, Address(CpuRegister(RSP), src.GetStackIndex()));
2702 CpuRegister out = locations->Out().AsRegister<CpuRegister>();
2708 __ xorl(out, out); // Clears upper bits too.
2720 codegen->Load64BitValue(out, 1ULL << value);
2722 codegen->Load32BitValue(out, 1 << value);
2747 __ movl(out, Immediate(1)); // Clears upper bits too.
2749 __ shlq(out, tmp);
2751 __ shll(out, tmp);
2755 __ xorl(out, out); // Clears upper bits too.
2774 __ movq(out, tmp);
2776 __ andq(out, tmp);
2778 __ movl(out, tmp);
2780 __ andl(out, tmp);
2830 CpuRegister out = locations->Out().AsRegister<CpuRegister>();
2841 codegen->Load32BitValue(out, value);
2848 __ bsrq(out, src.AsRegister<CpuRegister>());
2850 __ bsrl(out, src.AsRegister<CpuRegister>());
2854 __ bsrq(out, Address(CpuRegister(RSP), src.GetStackIndex()));
2857 __ bsrl(out, Address(CpuRegister(RSP), src.GetStackIndex()));
2865 __ xorl(out, Immediate(zero_value_result - 1));
2870 __ movl(out, Immediate(zero_value_result));
2904 CpuRegister out = locations->Out().AsRegister<CpuRegister>();
2915 codegen->Load32BitValue(out, value);
2922 __ bsfq(out, src.AsRegister<CpuRegister>());
2924 __ bsfl(out, src.AsRegister<CpuRegister>());
2928 __ bsfq(out, Address(CpuRegister(RSP), src.GetStackIndex()));
2931 __ bsfl(out, Address(CpuRegister(RSP), src.GetStackIndex()));
2939 __ movl(out, Immediate(zero_value_result));
2974 CpuRegister out = locations->Out().AsRegister<CpuRegister>();
2984 __ movl(out, Immediate(static_cast<int32_t>(address)));
2994 __ movl(Address(out, info.value_offset), Immediate(value));
2999 __ leal(out, Address(in, -info.low));
3000 __ cmpl(out, Immediate(info.high - info.low + 1));
3007 __ movl(out, Address(out, TIMES_4, data_offset + address));
3011 __ movl(out, Address(temp, out, TIMES_4, 0));
3013 __ MaybeUnpoisonHeapReference(out);
3022 __ movl(Address(out, info.value_offset), in);
3036 CpuRegister out = invoke->GetLocations()->Out().AsRegister<CpuRegister>();
3040 __ gs()->movl(out, address);
3041 __ testl(out, out);
