Lines Matching refs:BIT1
68 #define B_PCH_LPSS_DMAC_STSCMD_MSE BIT1 // Memory Space Enable
86 #define B_PCH_LPSS_DMAC_BAR_TYPE (BIT2 | BIT1) // Type
93 #define B_PCH_LPSS_DMAC_BAR1_TYPE (BIT2 | BIT1) // Type
122 #define B_PCH_LPSS_DMAC_PCS_PS (BIT1 | BIT0) // Power State
153 #define B_PCH_LPSS_I2C_STSCMD_MSE BIT1 // Memory Space Enable
171 #define B_PCH_LPSS_I2C_BAR_TYPE (BIT2 | BIT1) // Type
178 #define B_PCH_LPSS_I2C_BAR1_TYPE (BIT2 | BIT1) // Type
207 #define B_PCH_LPSS_I2C_PCS_PS (BIT1 | BIT0) // Power State
217 #define B_PCH_LPSS_I2C_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset
240 #define B_PCH_LPSS_PWM_STSCMD_MSE BIT1 // Memory Space Enable
258 #define B_PCH_LPSS_PWM_BAR_TYPE (BIT2 | BIT1) // Type
265 #define B_PCH_LPSS_PWM_BAR1_TYPE (BIT2 | BIT1) // Type
294 #define B_PCH_LPSS_PWM_PCS_PS (BIT1 | BIT0) // Power State
304 #define B_PCH_LPSS_PWM_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset
327 #define B_PCH_LPSS_HSUART_STSCMD_MSE BIT1 // Memory Space Enable
345 #define B_PCH_LPSS_HSUART_BAR_TYPE (BIT2 | BIT1) // Type
352 #define B_PCH_LPSS_HSUART_BAR1_TYPE (BIT2 | BIT1) // Type
381 #define B_PCH_LPSS_HSUART_PCS_PS (BIT1 | BIT0) // Power State
397 #define B_PCH_LPSS_HSUART_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset
419 #define B_PCH_LPSS_SPI_STSCMD_MSE BIT1 // Memory Space Enable
437 #define B_PCH_LPSS_SPI_BAR_TYPE (BIT2 | BIT1) // Type
444 #define B_PCH_LPSS_SPI_BAR1_TYPE (BIT2 | BIT1) // Type
473 #define B_PCH_LPSS_SPI_PCS_PS (BIT1 | BIT0) // Power State
489 #define B_PCH_LPSS_SPI_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset
