Lines Matching refs:BIT1
84 #define B_PCH_LPC_COMMAND_MSE BIT1 // Memory Space Enable
141 #define B_PCH_LPC_ACPI_BASE_EN BIT1 // Enable Bit
148 #define B_PCH_LPC_PMC_BASE_EN BIT1 // Enable Bit
153 #define B_PCH_LPC_GPIO_BASE_EN BIT1 // Enable Bit
160 #define B_PCH_LPC_IO_BASE_EN BIT1 // Enable Bit
167 #define B_PCH_LPC_ILB_BASE_EN BIT1 // Enable Bit
174 #define B_PCH_LPC_SPI_BASE_EN BIT1 // Enable Bit
181 #define B_PCH_LPC_MPHY_BASE_EN BIT1 // Enable Bit
188 #define B_PCH_LPC_PUNIT_BASE_EN BIT1 // Enable Bit
207 #define B_PCH_LPC_FWH_BIOS_DEC_E50 BIT1 // 50-5F Enable
243 #define B_PCH_LPC_CGC_PRILCG BIT1 // IOSF-PRI Local Clock Gating Disable
250 #define B_PCH_ILB_ACPI_CNT_SCI_IRQ_SEL (BIT2 | BIT1 | BIT0) // SCI IRQ Select
253 #define V_PCH_ILB_ACPI_CNT_SCI_IRQ_11 BIT1 // IRQ11
256 #define V_PCH_ILB_ACPI_CNT_SCI_IRQ_22 (BIT2 | BIT1) // IRQ22 (Only if APIC enabled)
257 #define V_PCH_ILB_ACPI_CNT_SCI_IRQ_23 (BIT2 | BIT1 | BIT0) // IRQ23 (Only if APIC enabled)
262 #define B_PCH_ILB_MC_D8254 BIT1 // Disable 8254
300 #define B_PCH_ILB_ULKMC_60WEN BIT1 // SMI on Port 60 Writes Enable
316 #define B_PCH_ILB_BIOS_CNTL_LE BIT1 // Lock Enable
383 #define B_PCH_ILB_DXXIR_IAR_MASK (BIT2 | BIT1 | BIT0) // INTA Mask
386 #define V_PCH_ILB_DXXIR_IAR_PIRQC BIT1 // INTA Mapping to IRQ C
387 #define V_PCH_ILB_DXXIR_IAR_PIRQD (BIT1 | BIT0) // INTA Mapping to IRQ D
390 #define V_PCH_ILB_DXXIR_IAR_PIRQG (BIT2 | BIT1) // INTA Mapping to IRQ G
391 #define V_PCH_ILB_DXXIR_IAR_PIRQH (BIT2 | BIT1 | BIT0) // INTA Mapping to IRQ H
398 #define B_PCH_ILB_RTC_CONF_UCMOS_LOCK BIT1 // Upper 128 Byte Lock
402 #define B_PCH_ILB_RTM_RTM1 (BIT2 | BIT1 | BIT0)
405 #define B_PCH_ILB_BCS_SMIWPEN BIT1 // SMI WPD Enable
409 #define B_PCH_ILB_LE_IRQ12C BIT1 // IRQ12 Cause
418 #define B_PCH_ILB_RTCC_DSWEN BIT1 // Deep Sleep Well Enable
433 #define B_PCH_ILB_DEF1_EETI BIT1 // 8259 Extend_EdgeTrig_IRQ
445 #define B_PCH_ILB_GNMI_GNMIE BIT1 // GPIO NMI Enable
452 #define B_PCH_ILB_LPCC_LPCCLK1EN BIT1 // Clock 1 Enable
508 #define B_PCH_ACPI_PM1_CNT_BM_RLD BIT1 // Treated as Scratchpad Bit
528 #define B_PCH_ACPI_GPE0a_STS_HOT_PLUG BIT1 // Hot Plug Status
545 #define B_PCH_ACPI_GPE0a_EN_HOT_PLUG BIT1 // Hot Plug Enable
564 #define B_PCH_SMI_EN_EOS BIT1 // End of SMI
629 #define B_PCH_UPRWC_WR_EN BIT1 // USB Per-Port Registers Write Enable
636 #define B_PCH_ACPI_GPE_CNTL_PCIE1_SCI_EN BIT1
679 #define B_PCH_PMC_PM_CFG_TIMING_T581 (BIT1 | BIT0) // Timing t581
689 #define B_PCH_PMC_PM_STS_SX_ENT_TO BIT1 // S3 / 4 / 5 Entry Timeout Status
731 #define B_PCH_PMC_GEN_PMCON_PER_SMI_SEL (BIT1 | BIT0) // Period SMI Select
740 #define B_PCH_PMC_SEC_STS_SEC (BIT3 | BIT2 | BIT1 | BIT0) // SEC Exclusion Cause
743 #define B_PCH_PMC_CRID_RID_SEL (BIT1 | BIT0) // Revision ID Select
777 #define B_PCH_PMC_FUNC_DIS_LPSS1_FUNC1 BIT1 // LPSS1 PWM #1 Disable
782 #define B_PCH_PMC_FUNC_DIS2_OTG_SS_PHY BIT1 // OTG Super Speed PHY Disable
795 #define B_PCH_PMC_GPI_ROUT_0 (BIT1 | BIT0)
814 #define B_PCH_PMC_PCC0_CLK_CTL (BIT1 | BIT0) // Clock Gating
818 #define B_PCH_PMC_PCC1_CLK_CTL (BIT1 | BIT0) // Clock Gating
822 #define B_PCH_PMC_PCC2_CLK_CTL (BIT1 | BIT0) // Clock Gating
826 #define B_PCH_PMC_PCC3_CLK_CTL (BIT1 | BIT0) // Clock Gating
830 #define B_PCH_PMC_PCC4_CLK_CTL (BIT1 | BIT0) // Clock Gating
834 #define B_PCH_PMC_PCC5_CLK_CTL (BIT1 | BIT0) // Clock Gating
868 #define B_PCH_PMC_PSS_PG_STS_SATA BIT1 // SATA
899 #define B_PCH_PMC_D3_STS_0_LPSS0F1 BIT1 // LPSS 0 Function 1
905 #define B_PCH_PMC_D3_STS_1_USH_SS BIT1 // USH SS
936 #define B_PCH_PMC_D3_STDBY_STS_0_LPSS0F1 BIT1 // LPSS 0 Function 1
942 #define B_PCH_PMC_D3_STDBY_STS_1_USH_SS BIT1 // USH SS
1030 #define B_PCH_NMI_SC_SPKR_DAT_EN BIT1 // Speaker Data Enable
1068 #define B_PCH_RTC_REGISTERA_RS (BIT3 | BIT2 | BIT1 | BIT0) // Rate Select
1093 #define B_PCH_RTC_REGISTERB_HF BIT1 // Hour Format 1: 24 mode; 0: 12 mode.
1101 #define B_PCH_RTC_REGISTERC_RESERVED (BIT3 | BIT2 | BIT1 | BIT0)
1120 #define B_PCH_PORT92_ALT_A20_GATE BIT1 // Alternate A20 Gate
1134 #define B_PCH_RST_CNT_SYS_RST BIT1
1175 #define B_PCH_PCH_HPET_GCFG_LRE BIT1 // Legacy Rout Enable
1180 #define B_PCH_PCH_HPET_GIS_T1 BIT1 // Timer 1 Status
1205 #define B_PCH_PCH_HPET_TXC_IT BIT1 // Timer Interrupt Type
