Lines Matching refs:BIT6
79 #define B_PCH_LPC_COMMAND_PER BIT6 // Parity Error Response Enable
204 #define B_PCH_LPC_FWH_BIOS_DEC_LEE BIT6 // Legacy E Segment Enable
373 #define B_PCH_ILB_DXXIR_IBR_MASK (BIT6 | BIT5 | BIT4) // INTB Mask
378 #define V_PCH_ILB_DXXIR_IBR_PIRQE BIT6 // INTB Mapping to IRQ E
379 #define V_PCH_ILB_DXXIR_IBR_PIRQF (BIT6 | BIT4) // INTB Mapping to IRQ F
380 #define V_PCH_ILB_DXXIR_IBR_PIRQG (BIT6 | BIT5) // INTB Mapping to IRQ G
381 #define V_PCH_ILB_DXXIR_IBR_PIRQH (BIT6 | BIT5 | BIT4) // INTB Mapping to IRQ H
413 #define B_PCH_ILB_RTCC_RTCB4 BIT6 // RTC Bias Resistor 4, Adds 480 Kohm
428 #define B_PCH_ILB_DEF1_ECWS BIT6 // 8254 Early CW Select
438 #define B_PCH_ILB_GNMI_NMI2SMIEN BIT6 // NMI to SMI Enable
456 #define B_PCH_ILB_IRQE_IRQ4TO7EN (BIT7 | BIT6 | BIT5 | BIT4) // IRQ4 - IRQ7 Enable
560 #define B_PCH_SMI_EN_SWSMI_TMR BIT6 // Software SMI Timer Enable
596 #define B_PCH_SMI_STS_SWSMI_TMR BIT6 // Software SMI Timer Status
671 #define B_PCH_PMC_PRSTS_SEC_WD_TMR_STS BIT6 // SEC Watchdog Timer Status
712 #define B_PCH_PMC_GEN_PMCON_SWSMI_RTSL (BIT7 | BIT6) // SWSMI Rate Select
772 #define B_PCH_PMC_FUNC_DIS_LPSS1_FUNC6 BIT6 // LPSS1 Spare #1 Disable
798 #define B_PCH_PMC_GPI_ROUT_3 (BIT7 | BIT6)
864 #define B_PCH_PMC_PSS_PG_STS_LPE BIT6 // LPE Audio
894 #define B_PCH_PMC_D3_STS_0_LPSS0F6 BIT6 // LPSS 0 Function 6
931 #define B_PCH_PMC_D3_STDBY_STS_0_LPSS0F6 BIT6 // LPSS 0 Function 6
1025 #define B_PCH_NMI_SC_IOCHK_NMI_STS BIT6 // IOCHK NMI Status
1061 #define B_PCH_RTC_REGISTERA_DV (BIT6 | BIT5 | BIT4) // Division Chain Select
1088 #define B_PCH_RTC_REGISTERB_PIE BIT6 // Periodic Interrupt Enable
1098 #define B_PCH_RTC_REGISTERC_PF BIT6 // Periodic Interrupt Flag
1105 #define B_PCH_RTC_REGISTERD_RESERVED BIT6
1200 #define B_PCH_PCH_HPET_TXC_TVS BIT6 // Timer Value Set
