Lines Matching refs:rvct
23 # ARM RVCT
24 CC.rvct := armcc
25 CFLAGS.rvct = -g --cpu=$(CPU) --fp16_format=ieee -Ono_special_regs_postregalloc -I.
26 LD.rvct := armlink
27 LDFLAGS.rvct := --cpu=$(CPU) --entry 0x2000
32 #LD.gccarm := $(LD.rvct)
33 #LDFLAGS.gccarm := $(LDFLAGS.rvct)
61 all: ref-rvct.qemu
63 check: check-rvct check-gccarm check-gccarm-rvct
65 # Building reference files with RVCT
66 REFOBJS.rvct = $(addsuffix .rvct.o, $(REFLIST) $(REFLIST_INT))
68 ref-rvct: $(REFRVCT)
69 ref-rvct.qemu: $(REFRVCT).qemu
71 check-rvct: $(REFRVCT)
72 diff $(REFRVCT) ref-rvct-all.txt
80 # don't have rvct
81 .PRECIOUS .INTERMEDIATE: compute_ref.rvct.o retarget.rvct.o \
82 InitCache.o Init.o $(REFOBJS.rvct)
84 compute_ref.axf: scatter.scat compute_ref.rvct.o retarget.rvct.o \
85 InitCache.o Init.o $(REFOBJS.rvct)
86 $(LD.rvct) $(LDFLAGS.rvct) --scatter $^ -o $@
88 compute_ref.rvct.o retarget.rvct.o: %.rvct.o: %.c
89 $(CC.rvct) $(CFLAGS.rvct) -c $^ -o $@ -DREFFILE=\"$(REFRVCT)\" -DGCCTESTS_FILE=\"expected_input4gcc.txt\"
91 ref_%.rvct.o: ref_%.c stm-arm-neon-ref.h
92 $(CC.rvct) $(CFLAGS.rvct) -c $< -o $@
95 $(CC.rvct) $(CFLAGS.rvct) -c $^ -o $@
104 diff $(REFGCCARM) ref-rvct-neon-nofp16.txt
116 REFGCCARM_RVCT=stm-arm-neon.gccarm-rvct
117 ref-gccarm-rvct: $(REFGCCARM_RVCT)
119 check-gccarm-rvct: $(REFGCCARM_RVCT)
120 diff $(REFGCCARM_RVCT) ref-rvct-neon-nofp16.txt
122 $(REFGCCARM_RVCT): compute_ref.gccarm-rvct
125 compute_ref.gccarm-rvct: scatter.scat compute_ref.gccarm-rvct.o \
126 retarget.rvct.o InitCache.o Init.o $(REFOBJS.gccarm)
127 $(LD.rvct) $(LDFLAGS.rvct) --no_strict_wchar_size --scatter $^ -o $@
129 compute_ref.gccarm-rvct.o: %.gccarm-rvct.o: %.c
