Lines Matching refs:Matrix
497 Matrix->unassign(LI);
512 Matrix->unassign(LI);
624 if (!Matrix->checkInterference(VirtReg, PhysReg))
663 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo, Matrix);
672 LiveIntervalUnion::Query subQ(&VirtReg, &Matrix->getLiveUnions()[*Units]);
728 if (Matrix->checkInterference(VirtReg, PhysReg) > LiveRegMatrix::IK_VirtReg)
746 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
822 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
834 Matrix->unassign(*Intf);
851 return !Matrix->isPhysRegUsed(PhysReg);
1664 if (!Matrix->query(const_cast<LiveInterval&>(SA->getParent()), *Units)
1676 Matrix->getLiveUnions()[*Units] .find(StartIdx);
1752 if (Matrix->checkRegMaskInterference(VirtReg)) {
1816 if (Matrix->checkRegMaskInterference(VirtReg, PhysReg))
1978 Matrix->invalidateVirtRegs();
2015 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
2115 if (Matrix->checkInterference(VirtReg, PhysReg) >
2145 Matrix->unassign(**It);
2151 Matrix->assign(VirtReg, PhysReg);
2161 Matrix->unassign(VirtReg);
2170 Matrix
2177 Matrix->unassign(**It);
2179 Matrix->assign(**It, ItPhysReg);
2208 Matrix->assign(*LI, PhysReg);
2392 Matrix->checkInterference(LI, PhysReg)))
2418 Matrix->unassign(LI);
2419 Matrix->assign(LI, PhysReg);
2484 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo, Matrix);
2609 IntfCache.init(MF, Matrix->getLiveUnions(), Indexes, LIS, TRI);
