Lines Matching refs:Classes
81 /// equivalence classes.
83 bool findComponents(IntEqClasses &Classes,
89 void distribute(const IntEqClasses &Classes,
94 void computeMainRangesFixFlags(const IntEqClasses &Classes,
99 void rewriteOperands(const IntEqClasses &Classes,
128 IntEqClasses Classes;
129 if (!findComponents(Classes, SubRangeInfos, LI))
137 DEBUG(dbgs() << PrintReg(Reg) << ": Found " << Classes.getNumClasses()
138 << " equivalence classes.\n");
140 for (unsigned I = 1, NumClasses = Classes.getNumClasses(); I < NumClasses;
149 rewriteOperands(Classes, SubRangeInfos, Intervals);
150 distribute(Classes, SubRangeInfos, Intervals);
151 computeMainRangesFixFlags(Classes, SubRangeInfos, Intervals);
155 bool RenameIndependentSubregs::findComponents(IntEqClasses &Classes,
174 // Next step: Build union-find structure over all subranges and merge classes
177 Classes.grow(NumComponents);
201 MergedID = MergedID == ~0u ? ID : Classes.join(MergedID, ID);
206 Classes.compress();
207 unsigned NumClasses = Classes.getNumClasses();
211 void RenameIndependentSubregs::rewriteOperands(const IntEqClasses &Classes,
241 ID = Classes[LocalID + SRInfo.Index];
248 // TODO: We could attempt to recompute new register classes while visiting
250 // classes than the original vreg.
253 void RenameIndependentSubregs::distribute(const IntEqClasses &Classes,
256 unsigned NumClasses = Classes.getNumClasses();
270 unsigned ID = Classes[LocalID + SRInfo.Index];
288 const IntEqClasses &Classes,
