Lines Matching full:ctlz
1385 case ISD::CTLZ: return visitCTLZ(N);
4871 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
4872 if (N1C && N0.getOpcode() == ISD::CTLZ &&
4881 // If all of the bits input the to ctlz node are known to be zero, then
4882 // the result of the ctlz is "32" and the result of the shift is one.
4886 // Otherwise, check to see if there is exactly one bit input to the ctlz.
4889 // could be set on input to the CTLZ node. If this bit is set, the SRL
4890 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
4987 // fold (ctlz c1) -> c2
4989 return DAG.getNode(ISD::CTLZ, SDLoc(N), VT, N0);
14403 // select_cc seteq X, 0, sizeof(X), ctlz(X) -> ctlz(X)
14404 // select_cc seteq X, 0, sizeof(X), ctlz_zero_undef(X) -> ctlz(X)
14407 // select_cc setne X, 0, ctlz(X), sizeof(X) -> ctlz(X)
14408 // select_cc setne X, 0, ctlz_zero_undef(X), sizeof(X) -> ctlz(X)
14427 // If the other operand is ctlz/ctlz_zero_undef of N0, and ctlz is
14428 // legal, combine to just ctlz.
14429 if ((Count.getOpcode() == ISD::CTLZ ||
14432 (!LegalOperations || TLI.isOperationLegal(ISD::CTLZ, VT)))
14433 return DAG.getNode(ISD::CTLZ, DL, VT, N0);
