Lines Matching refs:Shifted
370 SDNode *MatchRotatePosNeg(SDValue Shifted, SDValue Pos, SDValue Neg,
3991 // shifts of Shifted. If Neg == <operand size> - Pos then the OR reduces
3992 // to both (PosOpcode Shifted, Pos) and (NegOpcode Shifted, Neg), with the
3995 SDNode *DAGCombiner::MatchRotatePosNeg(SDValue Shifted, SDValue Pos,
4006 EVT VT = Shifted.getValueType();
4009 return DAG.getNode(HasPos ? PosOpcode : NegOpcode, DL, VT, Shifted,
4070 // If there is an AND of either shifted operand, apply it to the result.
4481 // that are shifted out by the inner shift in the first form. This means
4744 // Simplify, based on bits shifted out of the LHS.
6558 // Ensure that the shift amount is wide enough for the shifted value.
6763 /// If the result of a wider load is shifted to right of N bits and then
6833 // If the load is shifted left (and the result isn't shifted back right),
10662 // Moreover, if we shifted with a non-8-bits multiple, the slice
10816 // shifted by ByteShift and truncated down to NumBytes.
