Lines Matching refs:ResultReg
414 unsigned ResultReg =
417 if (!ResultReg)
421 updateValueMap(I, ResultReg);
448 unsigned ResultReg = fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0,
450 if (!ResultReg)
454 updateValueMap(I, ResultReg);
460 unsigned ResultReg = fastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
462 if (ResultReg) {
464 updateValueMap(I, ResultReg);
475 unsigned ResultReg = fastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
477 if (!ResultReg)
483 updateValueMap(I, ResultReg);
756 CLI.ResultReg = createResultReg(TLI.getRegClassFor(MVT::i64));
758 Ops.push_back(MachineOperand::CreateReg(CLI.ResultReg, /*IsDef=*/true));
851 updateValueMap(I, CLI.ResultReg, CLI.NumResultRegs);
1008 updateValueMap(CLI.CS->getInstruction(), CLI.ResultReg, CLI.NumResultRegs);
1222 unsigned ResultReg = getRegForValue(ResCI);
1223 if (!ResultReg)
1225 updateValueMap(II, ResultReg);
1229 unsigned ResultReg = getRegForValue(II->getArgOperand(0));
1230 if (!ResultReg)
1232 updateValueMap(II, ResultReg);
1269 unsigned ResultReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
1271 if (!ResultReg)
1274 updateValueMap(I, ResultReg);
1304 unsigned ResultReg = 0;
1310 ResultReg = createResultReg(DstClass);
1312 TII.get(TargetOpcode::COPY), ResultReg).addReg(Op0);
1317 if (!ResultReg)
1318 ResultReg = fastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0, Op0IsKill);
1320 if (!ResultReg)
1323 ResultReg);
1485 unsigned ResultReg = fastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(), ISD::FNEG,
1487 if (ResultReg) {
1488 updateValueMap(I, ResultReg);
1511 ResultReg = fastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(), ISD::BITCAST,
1513 if (!ResultReg)
1516 updateValueMap(I, ResultReg);
1538 unsigned ResultReg;
1541 ResultReg = I->second;
1543 ResultReg = FuncInfo.InitializeRegForValue(Op0);
1554 ResultReg += TLI.getNumRegisters(FuncInfo.Fn->getContext(), AggValueVTs[i]);
1556 updateValueMap(EVI, ResultReg);
1761 unsigned ResultReg = fastEmit_ri(VT, VT, Opcode, Op0, Op0IsKill, Imm);
1762 if (ResultReg)
1763 return ResultReg;
1808 unsigned ResultReg = createResultReg(RC);
1811 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg);
1812 return ResultReg;
1820 unsigned ResultReg = createResultReg(RC);
1824 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1830 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1833 return ResultReg;
1842 unsigned ResultReg = createResultReg(RC);
1847 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1855 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1857 return ResultReg;
1867 unsigned ResultReg = createResultReg(RC);
1873 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1883 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1885 return ResultReg;
1893 unsigned ResultReg = createResultReg(RC);
1897 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1905 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1907 return ResultReg;
1916 unsigned ResultReg = createResultReg(RC);
1920 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1930 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1932 return ResultReg;
1940 unsigned ResultReg = createResultReg(RC);
1943 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1949 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1951 return ResultReg;
1960 unsigned ResultReg = createResultReg(RC);
1965 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1975 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1977 return ResultReg;
1982 unsigned ResultReg = createResultReg(RC);
1986 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1991 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1993 return ResultReg;
1998 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
2004 ResultReg).addReg(Op0, getKillRegState(Op0IsKill), Idx);
2005 return ResultReg;
