Lines Matching defs:NewMIs
1305 SmallVector<MachineInstr *, 2> NewMIs;
1308 /*UnfoldStore=*/false, NewMIs)) {
1312 assert(NewMIs.size() == 2 &&
1315 NewMIs[1]->addRegisterKilled(Reg, TRI);
1319 MBB->insert(mi, NewMIs[0]);
1320 MBB->insert(mi, NewMIs[1]);
1322 DEBUG(dbgs() << "2addr: NEW LOAD: " << *NewMIs[0]
1323 << "2addr: NEW INST: " << *NewMIs[1]);
1326 unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA);
1327 unsigned NewSrcIdx = NewMIs[1]->findRegisterUseOperandIdx(regB);
1328 MachineBasicBlock::iterator NewMI = NewMIs[1];
1334 if (NewMIs[1]->getOperand(NewSrcIdx).isKill()) {
1344 if (NewMIs[0]->killsRegister(MO.getReg()))
1345 LV->replaceKillInstruction(MO.getReg(), MI, *NewMIs[0]);
1347 assert(NewMIs[1]->killsRegister(MO.getReg()) &&
1349 LV->replaceKillInstruction(MO.getReg(), MI, *NewMIs[1]);
1353 if (NewMIs[1]->registerDefIsDead(MO.getReg()))
1354 LV->addVirtualRegisterDead(MO.getReg(), *NewMIs[1]);
1356 assert(NewMIs[0]->registerDefIsDead(MO.getReg()) &&
1358 LV->addVirtualRegisterDead(MO.getReg(), *NewMIs[0]);
1363 LV->addVirtualRegisterKilled(Reg, *NewMIs[1]);
1378 MachineBasicBlock::iterator Begin(NewMIs[0]);
1379 MachineBasicBlock::iterator End(NewMIs[1]);
1383 mi = NewMIs[1];
1389 NewMIs[0]->eraseFromParent();
1390 NewMIs[1]->eraseFromParent();
