Lines Matching refs:ResultReg
323 unsigned ResultReg = createResultReg(&AArch64::GPR64spRegClass);
325 ResultReg)
329 return ResultReg;
346 unsigned ResultReg = createResultReg(RC);
348 ResultReg).addReg(ZeroReg, getKillRegState(true));
349 return ResultReg;
383 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
385 TII.get(TargetOpcode::COPY), ResultReg)
388 return ResultReg;
403 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
404 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
407 return ResultReg;
427 unsigned ResultReg;
435 ResultReg = createResultReg(&AArch64::GPR64RegClass);
437 ResultReg)
447 ResultReg = createResultReg(&AArch64::GPR64spRegClass);
449 ResultReg)
454 return ResultReg;
977 unsigned ResultReg = createResultReg(&AArch64::GPR64spRegClass);
979 ResultReg)
984 Addr.setReg(ResultReg);
988 unsigned ResultReg = 0;
992 ResultReg = emitAddSub_rx(/*UseAdd=*/true, MVT::i64, Addr.getReg(),
997 ResultReg = emitAddSub_rs(/*UseAdd=*/true, MVT::i64, Addr.getReg(),
1003 ResultReg = emitLSL_ri(MVT::i64, MVT::i32, Addr.getOffsetReg(),
1007 ResultReg = emitLSL_ri(MVT::i64, MVT::i32, Addr.getOffsetReg(),
1011 ResultReg = emitLSL_ri(MVT::i64, MVT::i64, Addr.getOffsetReg(),
1014 if (!ResultReg)
1017 Addr.setReg(ResultReg);
1026 unsigned ResultReg;
1029 ResultReg = emitAdd_ri_(MVT::i64, Addr.getReg(), /*IsKill=*/false, Offset);
1031 ResultReg = fastEmit_i(MVT::i64, MVT::i64, ISD::Constant, Offset);
1033 if (!ResultReg)
1035 Addr.setReg(ResultReg);
1133 unsigned ResultReg = 0;
1137 ResultReg = emitAddSub_ri(!UseAdd, RetVT, LHSReg, LHSIsKill, -Imm,
1140 ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, LHSIsKill, Imm, SetFlags,
1144 ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, LHSIsKill, 0, SetFlags,
1147 if (ResultReg)
1148 return ResultReg;
1188 ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg,
1191 if (ResultReg)
1192 return ResultReg;
1213 ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg,
1216 if (ResultReg)
1217 return ResultReg;
1254 unsigned ResultReg;
1256 ResultReg = createResultReg(RC);
1258 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
1263 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1266 return ResultReg;
1299 unsigned ResultReg;
1301 ResultReg = createResultReg(RC);
1303 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
1307 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1311 return ResultReg;
1339 unsigned ResultReg;
1341 ResultReg = createResultReg(RC);
1343 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
1348 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1352 return ResultReg;
1382 unsigned ResultReg;
1384 ResultReg = createResultReg(RC);
1386 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
1391 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1395 return ResultReg;
1480 unsigned ResultReg;
1482 ResultReg = emitAddSub_ri(false, VT, Op0, Op0IsKill, -Imm);
1484 ResultReg = emitAddSub_ri(true, VT, Op0, Op0IsKill, Imm);
1486 if (ResultReg)
1487 return ResultReg;
1493 ResultReg = emitAddSub_rr(true, VT, Op0, Op0IsKill, CReg, true);
1494 return ResultReg;
1542 unsigned ResultReg = 0;
1545 ResultReg = emitLogicalOp_ri(ISDOpc, RetVT, LHSReg, LHSIsKill, Imm);
1547 if (ResultReg)
1548 return ResultReg;
1567 ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, LHSIsKill, RHSReg,
1569 if (ResultReg)
1570 return ResultReg;
1583 ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, LHSIsKill, RHSReg,
1585 if (ResultReg)
1586 return ResultReg;
1596 ResultReg = fastEmit_rr(VT, VT, ISDOpc, LHSReg, LHSIsKill, RHSReg, RHSIsKill);
1599 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);
1601 return ResultReg;
1640 unsigned ResultReg =
1645 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);
1647 return ResultReg;
1683 unsigned ResultReg =
1688 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);
1690 return ResultReg;
1809 unsigned ResultReg = createResultReg(RC);
1811 TII.get(Opc), ResultReg);
1816 unsigned ANDReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, 1);
1818 ResultReg = ANDReg;
1828 .addReg(ResultReg, getKillRegState(true))
1830 ResultReg = Reg64;
1832 return ResultReg;
1843 unsigned ResultReg;
1848 ResultReg = emitAdd(VT, I->getOperand(0), I->getOperand(1));
1851 ResultReg = emitSub(VT, I->getOperand(0), I->getOperand(1));
1854 if (!ResultReg)
1857 updateValueMap(I, ResultReg);
1869 unsigned ResultReg;
1874 ResultReg = emitLogicalOp(ISD::AND, VT, I->getOperand(0), I->getOperand(1));
1877 ResultReg = emitLogicalOp(ISD::OR, VT, I->getOperand(0), I->getOperand(1));
1880 ResultReg = emitLogicalOp(ISD::XOR, VT, I->getOperand(0), I->getOperand(1));
1883 if (!ResultReg)
1886 updateValueMap(I, ResultReg);
1938 unsigned ResultReg =
1940 if (!ResultReg)
1966 ResultReg = std::prev(FuncInfo.InsertPt)->getOperand(0).getReg();
1968 ResultReg = fastEmitInst_extractsubreg(MVT::i32, ResultReg,
1972 updateValueMap(I, ResultReg);
1992 updateValueMap(IntExtVal, ResultReg);
1996 updateValueMap(I, ResultReg);
2446 unsigned ResultReg = 0;
2451 ResultReg = createResultReg(&AArch64::GPR32RegClass);
2453 TII.get(TargetOpcode::COPY), ResultReg)
2457 ResultReg = fastEmit_i(MVT::i32, MVT::i32, ISD::Constant, 1);
2461 if (ResultReg) {
2462 updateValueMap(I, ResultReg);
2470 ResultReg = createResultReg(&AArch64::GPR32RegClass);
2498 ResultReg)
2503 updateValueMap(I, ResultReg);
2512 ResultReg)
2517 updateValueMap(I, ResultReg);
2572 unsigned ResultReg = fastEmitInst_rr(Opc, &AArch64::GPR32RegClass, Src1Reg,
2574 updateValueMap(SI, ResultReg);
2702 unsigned ResultReg = fastEmitInst_rri(Opc, RC, Src1Reg, Src1IsKill, Src2Reg,
2704 updateValueMap(I, ResultReg);
2717 unsigned ResultReg = createResultReg(&AArch64::FPR64RegClass);
2719 ResultReg).addReg(Op);
2720 updateValueMap(I, ResultReg);
2733 unsigned ResultReg = createResultReg(&AArch64::FPR32RegClass);
2735 ResultReg).addReg(Op);
2736 updateValueMap(I, ResultReg);
2766 unsigned ResultReg = createResultReg(
2768 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
2770 updateValueMap(I, ResultReg);
2814 unsigned ResultReg = fastEmitInst_r(Opc, TLI.getRegClassFor(DestVT), SrcReg,
2816 updateValueMap(I, ResultReg);
2922 unsigned ResultReg = createResultReg(RC);
2924 TII.get(TargetOpcode::COPY), ResultReg)
2926 updateValueMap(&Arg, ResultReg);
3047 unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT));
3049 TII.get(TargetOpcode::COPY), ResultReg)
3053 CLI.ResultReg = ResultReg;
3220 unsigned ResultReg = emitLoad(VT, VT, Src);
3221 if (!ResultReg)
3224 if (!emitStore(VT, ResultReg, Dest))
3461 updateValueMap(II, CLI.ResultReg);
3484 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
3485 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
3487 updateValueMap(II, ResultReg);
3507 unsigned ResultReg = fastEmit_r(VT, VT, ISD::FSQRT, Op0Reg, Op0IsKill);
3508 if (!ResultReg)
3511 updateValueMap(II, ResultReg);
3801 unsigned ResultReg;
3822 ResultReg = emitAnd_ri(MVT::i32, Reg32, /*IsKill=*/true, Mask);
3823 assert(ResultReg && "Unexpected AND instruction emission failure.");
3825 ResultReg = createResultReg(&AArch64::GPR32RegClass);
3827 TII.get(TargetOpcode::COPY), ResultReg)
3831 updateValueMap(I, ResultReg);
3844 unsigned ResultReg = emitAnd_ri(MVT::i32, SrcReg, /*TODO:IsKill=*/false, 1);
3845 assert(ResultReg && "Unexpected AND instruction emission failure.");
3853 .addReg(ResultReg)
3855 ResultReg = Reg64;
3857 return ResultReg;
3927 unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg,
3930 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);
3931 return ResultReg;
3955 unsigned ResultReg = createResultReg(RC);
3957 TII.get(TargetOpcode::COPY), ResultReg)
3959 return ResultReg;
4034 unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg,
4037 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);
4038 return ResultReg;
4062 unsigned ResultReg = createResultReg(RC);
4064 TII.get(TargetOpcode::COPY), ResultReg)
4066 return ResultReg;
4155 unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg,
4158 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);
4159 return ResultReg;
4183 unsigned ResultReg = createResultReg(RC);
4185 TII.get(TargetOpcode::COPY), ResultReg)
4187 return ResultReg;
4431 unsigned ResultReg = createResultReg(&AArch64::GPR64RegClass);
4433 TII.get(AArch64::SUBREG_TO_REG), ResultReg)
4437 SrcReg = ResultReg;
4452 unsigned ResultReg = emitIntExt(SrcVT, SrcReg, RetVT, IsZExt);
4453 if (!ResultReg)
4456 updateValueMap(I, ResultReg);
4499 unsigned ResultReg = fastEmitInst_rrr(MSubOpc, RC, QuotReg, /*IsKill=*/true,
4502 updateValueMap(I, ResultReg);
4551 unsigned ResultReg =
4554 if (ResultReg) {
4555 updateValueMap(I, ResultReg);
4570 unsigned ResultReg = emitMul_rr(VT, Src0Reg, Src0IsKill, Src1Reg, Src1IsKill);
4572 if (!ResultReg)
4575 updateValueMap(I, ResultReg);
4588 unsigned ResultReg = 0;
4621 ResultReg = emitLSL_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);
4624 ResultReg = emitASR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);
4627 ResultReg = emitLSR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);
4630 if (!ResultReg)
4633 updateValueMap(I, ResultReg);
4647 unsigned ResultReg = 0;
4651 ResultReg = emitLSL_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill);
4654 ResultReg = emitASR_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill);
4657 ResultReg = emitLSR_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill);
4661 if (!ResultReg)
4664 updateValueMap(I, ResultReg);
4700 unsigned ResultReg = fastEmitInst_r(Opc, RC, Op0Reg, Op0IsKill);
4702 if (!ResultReg)
4705 updateValueMap(I, ResultReg);
4743 updateValueMap(I, CLI.ResultReg);
4767 unsigned ResultReg = emitASR_ri(VT, VT, Src0Reg, Src0IsKill, Lg2);
4768 if (!ResultReg)
4770 updateValueMap(I, ResultReg);
4801 unsigned ResultReg;
4803 ResultReg = emitAddSub_rs(/*UseAdd=*/false, VT, ZeroReg, /*IsKill=*/true,
4806 ResultReg = emitASR_ri(VT, VT, SelectReg, /*IsKill=*/true, Lg2);
4808 if (!ResultReg)
4811 updateValueMap(I, ResultReg);
