Lines Matching refs:EmitIntValue
297 OutStreamer->EmitIntValue(RsrcReg, 4);
298 OutStreamer->EmitIntValue(S_NUM_GPRS(MaxGPR + 1) |
300 OutStreamer->EmitIntValue(R_02880C_DB_SHADER_CONTROL, 4);
301 OutStreamer->EmitIntValue(S_02880C_KILL_ENABLE(killPixel), 4);
304 OutStreamer->EmitIntValue(R_0288E8_SQ_LDS_ALLOC, 4);
305 OutStreamer->EmitIntValue(alignTo(MFI->LDSSize, 4) >> 2, 4);
586 OutStreamer->EmitIntValue(R_00B848_COMPUTE_PGM_RSRC1, 4);
588 OutStreamer->EmitIntValue(KernelInfo.ComputePGMRSrc1, 4);
590 OutStreamer->EmitIntValue(R_00B84C_COMPUTE_PGM_RSRC2, 4);
591 OutStreamer->EmitIntValue(KernelInfo.ComputePGMRSrc2, 4);
593 OutStreamer->EmitIntValue(R_00B860_COMPUTE_TMPRING_SIZE, 4);
594 OutStreamer->EmitIntValue(S_00B860_WAVESIZE(KernelInfo.ScratchBlocks), 4);
599 OutStreamer->EmitIntValue(RsrcReg, 4);
600 OutStreamer->EmitIntValue(S_00B028_VGPRS(KernelInfo.VGPRBlocks) |
603 OutStreamer->EmitIntValue(R_0286E8_SPI_TMPRING_SIZE, 4);
604 OutStreamer->EmitIntValue(S_0286E8_WAVESIZE(KernelInfo.ScratchBlocks), 4);
609 OutStreamer->EmitIntValue(R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 4);
610 OutStreamer->EmitIntValue(S_00B02C_EXTRA_LDS_SIZE(KernelInfo.LDSBlocks), 4);
611 OutStreamer->EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
612 OutStreamer->EmitIntValue(MFI->PSInputEna, 4);
613 OutStreamer->EmitIntValue(R_0286D0_SPI_PS_INPUT_ADDR, 4);
614 OutStreamer->EmitIntValue(MFI->getPSInputAddr(), 4);
617 OutStreamer->EmitIntValue(R_SPILLED_SGPRS, 4);
618 OutStreamer->EmitIntValue(MFI->getNumSpilledSGPRs(), 4);
619 OutStreamer->EmitIntValue(R_SPILLED_VGPRS, 4);
620 OutStreamer->EmitIntValue(MFI->getNumSpilledVGPRs(), 4);
