Lines Matching refs:Operands
167 // When parsing operands, we can't always tell if something was meant to be
588 void cvtMubufImpl(MCInst &Inst, const OperandVector &Operands, bool IsAtomic, bool IsAtomicReturn);
647 OperandVector &Operands, MCStreamer &Out,
651 OperandMatchResultTy parseOperand(OperandVector &Operands, StringRef Mnemonic);
654 SMLoc NameLoc, OperandVector &Operands) override;
658 OperandVector &Operands,
661 OperandMatchResultTy parseNamedBit(const char *Name, OperandVector &Operands,
665 OperandMatchResultTy parseImm(OperandVector &Operands);
666 OperandMatchResultTy parseRegOrImm(OperandVector &Operands);
667 OperandMatchResultTy parseRegOrImmWithFPInputMods(OperandVector &Operands);
668 OperandMatchResultTy parseRegOrImmWithIntInputMods(OperandVector &Operands);
670 void cvtDSOffset01(MCInst &Inst, const OperandVector &Operands);
671 void cvtDS(MCInst &Inst, const OperandVector &Operands);
674 OperandMatchResultTy parseSWaitCntOps(OperandVector &Operands);
675 OperandMatchResultTy parseHwreg(OperandVector &Operands);
687 OperandMatchResultTy parseOptionalOperand(OperandVector &Operands);
689 OperandMatchResultTy parseSendMsgOp(OperandVector &Operands);
690 OperandMatchResultTy parseSOppBrTarget(OperandVector &Operands);
692 void cvtMubuf(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, false, false); }
693 void cvtMubufAtomic(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, true, false); }
694 void cvtMubufAtomicReturn(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, true, true); }
707 OperandMatchResultTy parseOModOperand(OperandVector &Operands);
709 void cvtId(MCInst &Inst, const OperandVector &Operands);
710 void cvtVOP3_2_mod(MCInst &Inst, const OperandVector &Operands);
711 void cvtVOP3(MCInst &Inst, const OperandVector &Operands);
713 void cvtMIMG(MCInst &Inst, const OperandVector &Operands);
714 void cvtMIMGAtomic(MCInst &Inst, const OperandVector &Operands);
716 OperandMatchResultTy parseDPPCtrl(OperandVector &Operands);
720 void cvtDPP(MCInst &Inst, const OperandVector &Operands);
722 OperandMatchResultTy parseSDWASel(OperandVector &Operands, StringRef Prefix,
724 OperandMatchResultTy parseSDWADstUnused(OperandVector &Operands);
725 void cvtSdwaVOP1(MCInst &Inst, const OperandVector &Operands);
726 void cvtSdwaVOP2(MCInst &Inst, const OperandVector &Operands);
727 void cvtSdwaVOPC(MCInst &Inst, const OperandVector &Operands);
728 void cvtSDWA(MCInst &Inst, const OperandVector &Operands,
968 AMDGPUAsmParser::parseImm(OperandVector &Operands) {
988 Operands.push_back(AMDGPUOperand::CreateImm(IntVal, S));
1001 Operands.push_back(
1012 AMDGPUAsmParser::parseRegOrImm(OperandVector &Operands) {
1013 auto res = parseImm(Operands);
1021 Operands.push_back(std::move(R));
1028 AMDGPUAsmParser::parseRegOrImmWithFPInputMods(OperandVector &Operands) {
1058 auto Res = parseRegOrImm(Operands);
1085 AMDGPUOperand &Op = static_cast<AMDGPUOperand &>(*Operands.back());
1092 AMDGPUAsmParser::parseRegOrImmWithIntInputMods(OperandVector &Operands) {
1105 auto Res = parseRegOrImm(Operands);
1121 AMDGPUOperand &Op = static_cast<AMDGPUOperand &>(*Operands.back());
1146 OperandVector &Operands,
1152 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
1167 if (ErrorInfo >= Operands.size()) {
1168 return Error(IDLoc, "too few operands for instruction");
1170 ErrorLoc = ((AMDGPUOperand &)*Operands[ErrorInfo]).getStartLoc();
1437 AMDGPUAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
1440 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
1446 // are appending default values to the Operands list. This is only done
1452 ResTy = parseRegOrImm(Operands);
1467 Operands.push_back(AMDGPUOperand::CreateExpr(Expr, S));
1471 Operands.push_back(AMDGPUOperand::CreateToken(Tok.getString(), Tok.getLoc()));
1502 SMLoc NameLoc, OperandVector &Operands) {
1505 Operands.push_back(AMDGPUOperand::CreateToken(Name, NameLoc));
1508 AMDGPUAsmParser::OperandMatchResultTy Res = parseOperand(Operands, Name);
1565 AMDGPUAsmParser::parseIntWithPrefix(const char *Prefix, OperandVector &Operands,
1580 Operands.push_back(AMDGPUOperand::CreateImm(Value, S, ImmTy));
1585 AMDGPUAsmParser::parseNamedBit(const char *Name, OperandVector &Operands,
1612 Operands.push_back(AMDGPUOperand::CreateImm(Bit, S, ImmTy));
1618 void addOptionalImmOperand(MCInst& Inst, const OperandVector& Operands,
1624 ((AMDGPUOperand &)*Operands[Idx]).addImmOperands(Inst, 1);
1659 const OperandVector &Operands) {
1663 for (unsigned i = 1, e = Operands.size(); i != e; ++i) {
1664 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
1676 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOffset0);
1677 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOffset1);
1678 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyGDS);
1683 void AMDGPUAsmParser::cvtDS(MCInst &Inst, const OperandVector &Operands) {
1688 for (unsigned i = 1, e = Operands.size(); i != e; ++i) {
1689 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
1706 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOffset);
1707 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyGDS);
1710 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyGDS);
1764 AMDGPUAsmParser::parseSWaitCntOps(OperandVector &Operands) {
1787 Operands.push_back(AMDGPUOperand::CreateImm(CntVal, S));
1853 AMDGPUAsmParser::parseHwreg(OperandVector &Operands) {
1892 Operands.push_back(AMDGPUOperand::CreateImm(Imm16Val, S, AMDGPUOperand::ImmTyHwreg));
2001 AMDGPUAsmParser::parseSendMsgOp(OperandVector &Operands) {
2075 Operands.push_back(AMDGPUOperand::CreateImm(Imm16Val, S, AMDGPUOperand::ImmTySendMsg));
2088 AMDGPUAsmParser::parseSOppBrTarget(OperandVector &Operands) {
2097 Operands.push_back(AMDGPUOperand::CreateImm(Imm, S));
2102 Operands.push_back(AMDGPUOperand::CreateExpr(
2127 const OperandVector &Operands,
2132 for (unsigned i = 1, e = Operands.size(); i != e; ++i) {
2133 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
2148 // asm string. There are no MCInst operands for these.
2164 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOffset);
2166 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyGLC);
2168 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySLC);
2169 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyTFE);
2176 void AMDGPUAsmParser::cvtMIMG(MCInst &Inst, const OperandVector &Operands) {
2180 ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
2185 for (unsigned E = Operands.size(); I != E; ++I) {
2186 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
2199 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDMask);
2200 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyUNorm);
2201 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyGLC);
2202 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDA);
2203 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyR128);
2204 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyTFE);
2205 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyLWE);
2206 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySLC);
2209 void AMDGPUAsmParser::cvtMIMGAtomic(MCInst &Inst, const OperandVector &Operands) {
2213 ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
2217 ((AMDGPUOperand &)*Operands[I]).addRegOperands(Inst, 1);
2221 for (unsigned E = Operands.size(); I != E; ++I) {
2222 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
2235 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDMask);
2236 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyUNorm);
2237 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyGLC);
2238 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDA);
2239 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyR128);
2240 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyTFE);
2241 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyLWE);
2242 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySLC);
2327 // Note: the order in this table matches the order of operands in AsmString.
2355 AMDGPUAsmParser::OperandMatchResultTy AMDGPUAsmParser::parseOptionalOperand(OperandVector &Operands) {
2360 res = parseNamedBit(Op.Name, Operands, Op.Type);
2362 res = parseOModOperand(Operands);
2366 res = parseSDWASel(Operands, Op.Name, Op.Type);
2368 res = parseSDWADstUnused(Operands);
2370 res = parseIntWithPrefix(Op.Name, Operands, Op.Type, Op.ConvertResult);
2379 AMDGPUAsmParser::OperandMatchResultTy AMDGPUAsmParser::parseOModOperand(OperandVector &Operands)
2383 return parseIntWithPrefix("mul", Operands, AMDGPUOperand::ImmTyOModSI, ConvertOmodMul);
2385 return parseIntWithPrefix("div", Operands, AMDGPUOperand::ImmTyOModSI, ConvertOmodDiv);
2391 void AMDGPUAsmParser::cvtId(MCInst &Inst, const OperandVector &Operands) {
2395 ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
2397 for (unsigned E = Operands.size(); I != E; ++I)
2398 ((AMDGPUOperand &)*Operands[I]).addRegOrImmOperands(Inst, 1);
2401 void AMDGPUAsmParser::cvtVOP3_2_mod(MCInst &Inst, const OperandVector &Operands) {
2404 cvtVOP3(Inst, Operands);
2406 cvtId(Inst, Operands);
2410 void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands) {
2415 ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
2418 for (unsigned E = Operands.size(); I != E; ++I) {
2419 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
2430 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI);
2431 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOModSI);
2459 AMDGPUAsmParser::parseDPPCtrl(OperandVector &Operands) {
2567 Operands.push_back(AMDGPUOperand::CreateImm(Int, S,
2584 void AMDGPUAsmParser::cvtDPP(MCInst &Inst, const OperandVector &Operands) {
2590 ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
2593 for (unsigned E = Operands.size(); I != E; ++I) {
2594 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
2609 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppRowMask, 0xf);
2610 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBankMask, 0xf);
2611 addOptionalImmOperand(Inst, Operands
2619 AMDGPUAsmParser::parseSDWASel(OperandVector &Operands, StringRef Prefix,
2646 Operands.push_back(AMDGPUOperand::CreateImm(Int, S, Type));
2651 AMDGPUAsmParser::parseSDWADstUnused(OperandVector &Operands) {
2673 Operands.push_back(AMDGPUOperand::CreateImm(Int, S,
2678 void AMDGPUAsmParser::cvtSdwaVOP1(MCInst &Inst, const OperandVector &Operands) {
2679 cvtSDWA(Inst, Operands, SIInstrFlags::VOP1);
2682 void AMDGPUAsmParser::cvtSdwaVOP2(MCInst &Inst, const OperandVector &Operands) {
2683 cvtSDWA(Inst, Operands, SIInstrFlags::VOP2);
2686 void AMDGPUAsmParser::cvtSdwaVOPC(MCInst &Inst, const OperandVector &Operands) {
2687 cvtSDWA(Inst, Operands, SIInstrFlags::VOPC);
2690 void AMDGPUAsmParser::cvtSDWA(MCInst &Inst, const OperandVector &Operands,
2697 ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
2700 for (unsigned E = Operands.size(); I != E; ++I) {
2701 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
2718 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI, 0);
2726 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaDstSel, 6);
2727 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaDstUnused, 2);
2728 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc0Sel, 6);
2732 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaDstSel, 6);
2733 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaDstUnused, 2);
2734 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc0Sel, 6);
2735 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc1Sel, 6);
2739 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc0Sel, 6);
2740 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc1Sel, 6);
2763 // Tokens like "glc" would be parsed as immediate operands in ParseOperand().
2780 // When operands have expression values, they will return true for isToken,
