Lines Matching refs:TII
60 const R600InstrInfo *TII;
75 if (!TII->isALUInstr(I->getOpcode()) && !I->isBundle())
87 if (TII->isPredicated(*BI))
89 int OperandIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::write);
92 int DstIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::dst);
97 if (isTrans || TII->isTransOnly(*BI)) {
139 int OperandIdx = TII->getOperandIdx(MI.getOpcode(), Ops[i]);
153 TII(ST.getInstrInfo()),
154 TRI(TII->getRegisterInfo()) {
172 if (TII->isVector(MI))
174 if (!TII->isALUInstr(MI.getOpcode()))
180 return TII->isLDSInstr(MI.getOpcode());
190 int OpI = TII->getOperandIdx(MII->getOpcode(), AMDGPU::OpName::pred_sel),
191 OpJ = TII->getOperandIdx(MIJ->getOpcode(), AMDGPU::OpName::pred_sel);
211 TII->definesAddressRegister(*MII) || TII->definesAddressRegister(*MIJ);
213 TII->usesAddressRegister(*MII) || TII->usesAddressRegister(*MIJ);
225 unsigned LastOp = TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::last);
233 isTransSlot = TII->isTransOnly(MI);
240 !TII->isVectorOnly(MI) && VLIW5) {
254 if (!TII->fitsConstReadLimitations(CurrentPacketMIs)) {
270 if (!TII->fitsReadPortLimitations(CurrentPacketMIs,
287 if (isTransSlot && TII->readsLDSSrcReg(MI))
305 unsigned Op = TII->getOperandIdx(MI->getOpcode(),
310 TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::bank_swizzle);
322 if (TII->isTransOnly(MI))
330 const R600InstrInfo *TII = ST.getInstrInfo();
381 if (TII->isSchedulingBoundary(*std::prev(I), &*MBB, Fn))
