Lines Matching refs:EXEC
17 /// by writting to the 64-bit EXEC register (each bit corresponds to a
19 /// to its bit of the VCC register (like EXEC VCC is 64-bits, one for each
21 /// EXEC to update the predicates.
33 /// %SGPR0 = S_AND_SAVEEXEC_B64 %VCC // Save and update the exec mask
34 /// %SGPR0 = S_XOR_B64 %SGPR0, %EXEC // Clear live bits from saved exec mask
38 /// // EXEC are zero.
42 /// %SGPR0 = S_OR_SAVEEXEC_B64 %EXEC // Restore the exec mask for the Then block
43 /// %EXEC = S_XOR_B64 %SGPR0, %EXEC // Clear live bits from saved exec mask
48 /// %EXEC = S_OR_B64 %EXEC, %SGPR0 // Re-enable saved exec mask bits
176 // when EXEC = 0. We should skip the loop lest it becomes infinite.
224 // If the exec mask is non-zero, skip the next two instructions
230 // Exec mask is zero: Export to NULL target...
258 .addReg(AMDGPU::EXEC)
279 .addReg(Src); // Saved EXEC
282 // Adjust the saved exec to account for the modifications during the flow
286 .addReg(AMDGPU::EXEC)
290 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC)
291 .addReg(AMDGPU::EXEC)
312 .addReg(AMDGPU::EXEC)
353 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_ANDN2_B64), AMDGPU::EXEC)
354 .addReg(AMDGPU::EXEC)
369 TII->get(AMDGPU::S_OR_B64), AMDGPU::EXEC)
370 .addReg(AMDGPU::EXEC)
396 // Clear this thread from the exec mask if the operand is negative
398 // Constant operand: Set exec mask to 0 or do nothing
400 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B64), AMDGPU::EXEC)
464 // Update EXEC, save the original EXEC value to VCC
477 // Update EXEC, switch all done bits to 0 and all todo bits to 1
478 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC)
479 .addReg(AMDGPU::EXEC)
556 // Save the EXEC mask
558 .addReg(AMDGPU::EXEC);
582 BuildMI(*RemainderBB, First, DL, TII->get(AMDGPU::S_MOV_B64), AMDGPU::EXEC)
716 if (I->modifiesRegister(AMDGPU::EXEC, TRI))
