Lines Matching refs:VCC
19 /// to its bit of the VCC register (like EXEC VCC is 64-bits, one for each
20 /// Vector ALU) and then the ScalarALU will AND the VCC register with the
24 /// %VCC = V_CMP_GT_F32 %VGPR1, %VGPR2
25 /// %SGPR0 = SI_IF %VCC
33 /// %SGPR0 = S_AND_SAVEEXEC_B64 %VCC // Save and update the exec mask
252 unsigned Vcc = MI.getOperand(1).getReg();
255 .addReg(Vcc);
323 unsigned Vcc = MI.getOperand(1).getReg();
327 .addReg(Vcc)
451 // Read the next variant into VCC (lower 32 bits) <- also loop target
455 // Move index from VCC into M0
464 // Update EXEC, save the original EXEC value to VCC
465 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), AMDGPU::VCC)
466 .addReg(AMDGPU::VCC);
480 .addReg(AMDGPU::VCC);
