Lines Matching defs:Src0
113 // We don't need to check src0, all input types are legal, so just make sure
114 // src0 isn't using any modifiers.
138 int Src0Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src0);
139 MachineOperand &Src0 = MI.getOperand(Src0Idx);
141 // Only one literal constant is allowed per instruction, so if src0 is a
143 if (Src0.isImm() &&
144 TII->isLiteralConstant(Src0, TII->getOpSize(MI, Src0Idx)))
147 // Literal constants and SGPRs can only be used in Src0, so if Src0 is an
150 if (Src0.isReg() && !isVGPR(&Src0, TRI, MRI))
153 // Try to fold Src0
154 if (Src0.isReg() && MRI.hasOneUse(Src0.getReg())) {
155 unsigned Reg = Src0.getReg();
162 Src0.ChangeToImmediate(MovSrc.getImm());
174 // We have failed to fold src0, so commute the instruction and try again.
276 const MachineOperand &Src0 = MI.getOperand(1);
283 Src0.isReg()) {
284 MRI.setRegAllocationHint(Dest.getReg(), 0, Src0.getReg());
288 if (Src0.isReg() && Src0.getReg() == Dest.getReg()) {
379 Inst32.addOperand(*TII->getNamedOperand(MI, AMDGPU::OpName::src0));
