Cross Reference: /external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

Lines Matching refs:getSubReg
821   if (TRI->regsOverlap(SrcReg, TRI->getSubReg(DestReg, BeginIdx))) {
829     unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i * Spacing);
830     unsigned Src = TRI->getSubReg(SrcReg, BeginIdx + i * Spacing);
859     return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
1024     if (MI.getOperand(0).isFI() && MI.getOperand(2).getSubReg() == 0) {
1030     if (MI.getOperand(1).isFI() && MI.getOperand(0).getSubReg() == 0) {
1206     if (MI.getOperand(1).isFI() && MI.getOperand(0).getSubReg() == 0) {
1212     if (MI.getOperand(1).isFI() && MI.getOperand(0).getSubReg() == 0) {
4258   ImplicitSReg = TRI->getSubReg(DReg,
4526     if (!MO.getSubReg() || MI.readsVirtualRegister(Reg))
4610         RegSubRegPairAndIdx(MOReg->getReg(), MOReg->getSubReg(), ARM::ssub_0));
4614         RegSubRegPairAndIdx(MOReg->getReg(), MOReg->getSubReg(), ARM::ssub_1));
4634     InputReg.SubReg = MOReg.getSubReg();
4654     BaseReg.SubReg = MOBaseReg.getSubReg();
4657     InsertedReg.SubReg = MOInsertedReg.getSubReg();
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