Lines Matching refs:ResultReg
165 bool ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
281 unsigned ResultReg = createResultReg(RC);
289 ResultReg).addReg(Op0, Op0IsKill * RegState::Kill));
294 TII.get(TargetOpcode::COPY), ResultReg)
297 return ResultReg;
304 unsigned ResultReg = createResultReg(RC);
314 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
322 TII.get(TargetOpcode::COPY), ResultReg)
325 return ResultReg;
332 unsigned ResultReg = createResultReg(RC);
340 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
348 TII.get(TargetOpcode::COPY), ResultReg)
351 return ResultReg;
359 unsigned ResultReg = createResultReg(RC);
368 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
378 TII.get(TargetOpcode::COPY), ResultReg)
381 return ResultReg;
387 unsigned ResultReg = createResultReg(RC);
392 ResultReg).addImm(Imm));
397 TII.get(TargetOpcode::COPY), ResultReg)
400 return ResultReg;
507 unsigned ResultReg = 0;
509 ResultReg = fastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
511 if (ResultReg)
512 return ResultReg;
525 ResultReg = createResultReg(TLI.getRegClassFor(VT));
528 TII.get(ARM::t2LDRpci), ResultReg)
532 ResultReg = constrainOperandRegClass(TII.get(ARM::LDRcp), ResultReg, 0);
534 TII.get(ARM::LDRcp), ResultReg)
538 return ResultReg;
680 unsigned ResultReg = createResultReg(RC);
681 ResultReg = constrainOperandRegClass(TII.get(Opc), ResultReg, 0);
684 TII.get(Opc), ResultReg)
687 return ResultReg;
855 unsigned ResultReg = createResultReg(RC);
858 ResultReg)
861 Addr.Base.Reg = ResultReg;
919 bool ARMFastISel::ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
1003 ResultReg = createResultReg(RC);
1004 assert (ResultReg > 255 && "Expected an allocated virtual register.");
1006 TII.get(Opc), ResultReg);
1015 .addReg(ResultReg));
1016 ResultReg = MoveReg;
1050 unsigned ResultReg;
1051 if (!ARMEmitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
1053 updateValueMap(I, ResultReg);
1571 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
1573 TII.get(Opc), ResultReg).addReg(FP));
1574 updateValueMap(I, ResultReg);
1597 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1599 TII.get(Opc), ResultReg).addReg(Op));
1603 unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg);
1663 unsigned ResultReg = createResultReg(RC);
1668 ResultReg)
1676 ResultReg)
1682 updateValueMap(I, ResultReg);
1766 unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass);
1770 TII.get(Opc), ResultReg)
1772 updateValueMap(I, ResultReg);
1814 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy));
1816 TII.get(Opc), ResultReg)
1818 updateValueMap(I, ResultReg);
2037 unsigned ResultReg = createResultReg(DstRC);
2039 TII.get(ARM::VMOVDRR), ResultReg)
2047 updateValueMap(I, ResultReg);
2058 unsigned ResultReg = createResultReg(DstRC);
2061 ResultReg).addReg(RVLocs[0].getLocReg());
2065 updateValueMap(I, ResultReg);
2455 unsigned ResultReg;
2456 RV = ARMEmitLoad(VT, ResultReg, Src);
2458 RV = ARMEmitStore(VT, ResultReg, Dest);
2684 unsigned ResultReg;
2700 ResultReg = createResultReg(RC);
2707 *FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opcode), ResultReg);
2715 SrcReg = ResultReg;
2718 return ResultReg;
2740 unsigned ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, isZExt);
2741 if (ResultReg == 0) return false;
2742 updateValueMap(I, ResultReg);
2782 unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass);
2783 if(ResultReg == 0) return false;
2786 TII.get(Opc), ResultReg)
2797 updateValueMap(I, ResultReg);
2927 unsigned ResultReg = MI->getOperand(0).getReg();
2928 if (!ARMEmitLoad(VT, ResultReg, Addr, LI->getAlignment(), isZExt, false))
3048 unsigned ResultReg = createResultReg(RC);
3051 ResultReg).addReg(DstReg, getKillRegState(true));
3052 updateValueMap(&*I, ResultReg);
