Lines Matching refs:RR
314 uint16_t BT::MachineEvaluator::getRegBitWidth(const RegisterRef &RR) const {
320 // 1. find a physical register PhysR from the same class as RR.Reg,
321 // 2. find a physical register PhysS that corresponds to PhysR:RR.Sub,
324 if (TargetRegisterInfo::isVirtualRegister(RR.Reg)) {
325 const TargetRegisterClass *VC = MRI.getRegClass(RR.Reg);
329 assert(TargetRegisterInfo::isPhysicalRegister(RR.Reg));
330 PhysR = RR.Reg;
333 unsigned PhysS = (RR.Sub == 0) ? PhysR : TRI.getSubReg(PhysR, RR.Sub);
340 BT::RegisterCell BT::MachineEvaluator::getCell(const RegisterRef &RR,
342 uint16_t BW = getRegBitWidth(RR);
346 if (TargetRegisterInfo::isPhysicalRegister(RR.Reg))
349 assert(TargetRegisterInfo::isVirtualRegister(RR.Reg));
352 const TargetRegisterClass *C = MRI.getRegClass(RR.Reg);
356 CellMapType::const_iterator F = M.find(RR.Reg);
358 if (!RR.Sub)
360 BitMask M = mask(RR.Reg, RR.Sub);
368 void BT::MachineEvaluator::putCell(const RegisterRef &RR, RegisterCell RC,
373 if (!TargetRegisterInfo::isVirtualRegister(RR.Reg))
375 assert(RR.Sub == 0 && "Unexpected sub-register in definition");
380 RC[i].RefI = BitRef(RR.Reg, i);
382 M[RR.Reg] = RC;
995 BT::RegisterCell BT::get(RegisterRef RR) const {
996 return ME.getCell(RR, Map);
1000 void BT::put(RegisterRef RR, const RegisterCell &RC) {
1001 ME.putCell(RR, RC, Map);
