Lines Matching refs:HexagonInstrInfo
1 //===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===//
14 #include "HexagonInstrInfo.h"
101 void HexagonInstrInfo::anchor() {}
103 HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST)
234 unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
301 unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
373 bool HexagonInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
544 unsigned HexagonInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
564 unsigned HexagonInstrInfo::InsertBranch(MachineBasicBlock &MBB,
665 bool HexagonInstrInfo::analyzeLoop(MachineLoop &L,
683 unsigned HexagonInstrInfo::reduceLoopCount(MachineBasicBlock &MBB,
740 bool HexagonInstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB,
747 bool HexagonInstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB,
755 bool HexagonInstrInfo::isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
760 void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
866 void HexagonInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
928 void HexagonInstrInfo::loadRegFromStackSlot(
987 bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
1323 bool HexagonInstrInfo::ReverseBranchCondition(
1339 void HexagonInstrInfo::insertNoop(MachineBasicBlock &MBB,
1354 bool HexagonInstrInfo::isPredicated(const MachineInstr &MI) const {
1360 bool HexagonInstrInfo::PredicateInstruction(
1412 bool HexagonInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
1419 bool HexagonInstrInfo::DefinesPredicate(
1436 bool HexagonInstrInfo::isPredicable(MachineInstr &MI) const {
1440 bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr &MI,
1486 unsigned HexagonInstrInfo::getInlineAsmLength(const char *Str,
1513 HexagonInstrInfo::CreateTargetPostRAHazardRecognizer(
1523 bool HexagonInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
1608 unsigned HexagonInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
1615 DFAPacketizer *HexagonInstrInfo::CreateTargetScheduleState(
1626 bool HexagonInstrInfo::areMemAccessesTriviallyDisjoint(
1668 bool HexagonInstrInfo::getIncrementValue(const MachineInstr *MI,
1683 unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const {
1701 bool HexagonInstrInfo::isAbsoluteSet(const MachineInstr* MI) const {
1706 bool HexagonInstrInfo::isAccumulator(const MachineInstr *MI) const {
1712 bool HexagonInstrInfo::isComplex(const MachineInstr *MI) const {
1715 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
1734 bool HexagonInstrInfo::isCompoundBranchInstr(const MachineInstr *MI) const {
1739 bool HexagonInstrInfo::isCondInst(const MachineInstr *MI) const {
1750 bool HexagonInstrInfo::isConditionalALU32(const MachineInstr* MI) const {
1810 bool HexagonInstrInfo::isConditionalLoad(const MachineInstr* MI) const {
1824 bool HexagonInstrInfo::isConditionalStore(const MachineInstr* MI) const {
1878 bool HexagonInstrInfo::isConditionalTransfer(const MachineInstr *MI) const {
1901 bool HexagonInstrInfo::isConstExtended(const MachineInstr *MI) const {
1948 bool HexagonInstrInfo::isDeallocRet(const MachineInstr *MI) const {
1964 bool HexagonInstrInfo::isDependent(const MachineInstr *ProdMI,
2002 bool HexagonInstrInfo::isDotCurInst(const MachineInstr* MI) const {
2016 bool HexagonInstrInfo::isDotNewInst(const MachineInstr* MI) const {
2025 bool HexagonInstrInfo::isDuplexPair(const MachineInstr *MIa,
2033 bool HexagonInstrInfo::isEarlySourceInstr(const MachineInstr *MI) const {
2048 bool HexagonInstrInfo::isEndLoopN(unsigned Opcode) const {
2054 bool HexagonInstrInfo::isExpr(unsigned OpType) const {
2069 bool HexagonInstrInfo::isExtendable(const MachineInstr *MI) const {
2091 bool HexagonInstrInfo::isExtended(const MachineInstr *MI) const {
2107 bool HexagonInstrInfo::isFloat(const MachineInstr *MI) const {
2115 bool HexagonInstrInfo::isHVXMemWithAIndirect(const MachineInstr *I,
2125 bool HexagonInstrInfo::isIndirectCall(const MachineInstr *MI) const {
2136 bool HexagonInstrInfo::isIndirectL4Return(const MachineInstr *MI) const {
2151 bool HexagonInstrInfo::isJumpR(const MachineInstr *MI) const {
2170 bool HexagonInstrInfo::isJumpWithinBranchRange(const MachineInstr *MI,
2211 bool HexagonInstrInfo::isLateInstrFeedsEarlyInstr(const MachineInstr *LRMI,
2233 bool HexagonInstrInfo::isLateResultInstr(const MachineInstr *MI) const {
2273 bool HexagonInstrInfo::isLateSourceInstr(const MachineInstr *MI) const {
2283 bool HexagonInstrInfo::isLoopN(const MachineInstr *MI) const {
2296 bool HexagonInstrInfo::isMemOp(const MachineInstr *MI) const {
2329 bool HexagonInstrInfo::isNewValue(const MachineInstr* MI) const {
2335 bool HexagonInstrInfo::isNewValue(unsigned Opcode) const {
2341 bool HexagonInstrInfo::isNewValueInst(const MachineInstr *MI) const {
2346 bool HexagonInstrInfo::isNewValueJump(const MachineInstr *MI) const {
2351 bool HexagonInstrInfo::isNewValueJump(unsigned Opcode) const {
2356 bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const {
2362 bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const {
2369 bool HexagonInstrInfo::isOperandExtended(const MachineInstr *MI,
2377 bool HexagonInstrInfo::isPostIncrement(const MachineInstr* MI) const {
2382 bool HexagonInstrInfo::isPredicatedNew(const MachineInstr &MI) const {
2389 bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const {
2396 bool HexagonInstrInfo::isPredicatedTrue(const MachineInstr &MI) const {
2403 bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode) const {
2412 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const {
2418 bool HexagonInstrInfo::isPredicateLate(unsigned Opcode) const {
2424 bool HexagonInstrInfo::isPredictedTaken(unsigned Opcode) const {
2432 bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr *MI) const {
2439 bool HexagonInstrInfo::isSignExtendingLoad(const MachineInstr &MI) const {
2518 bool HexagonInstrInfo::isSolo(const MachineInstr* MI) const {
2524 bool HexagonInstrInfo::isSpillPredRegOp(const MachineInstr *MI) const {
2535 bool HexagonInstrInfo::isTailCall(const MachineInstr *MI) const {
2547 bool HexagonInstrInfo::isTC1(const MachineInstr *MI) const {
2566 bool HexagonInstrInfo::isTC2(const MachineInstr *MI) const {
2583 bool HexagonInstrInfo::isTC2Early(const MachineInstr *MI) const {
2604 bool HexagonInstrInfo::isTC4x(const MachineInstr *MI) const {
2613 bool HexagonInstrInfo::isV60VectorInstruction(const MachineInstr *MI) const {
2624 bool HexagonInstrInfo::isValidAutoIncImm(const EVT VT, const int Offset) const {
2661 bool HexagonInstrInfo::isValidOffset(unsigned Opcode, int Offset,
2822 bool HexagonInstrInfo::isVecAcc(const MachineInstr *MI) const {
2827 bool HexagonInstrInfo::isVecALU(const MachineInstr *MI) const {
2838 bool HexagonInstrInfo::isVecUsableNextPacket(const MachineInstr *ProdMI,
2852 bool HexagonInstrInfo::isZeroExtendingLoad(const MachineInstr &MI) const {
2932 bool HexagonInstrInfo::addLatencyToSchedule(const MachineInstr *MI1,
2942 bool HexagonInstrInfo::getMemOpBaseRegImmOfs(MachineInstr &LdSt,
2954 bool HexagonInstrInfo::canExecuteInBundle(const MachineInstr *First,
2975 bool HexagonInstrInfo::hasEHLabel(const MachineBasicBlock *B) const {
2985 bool HexagonInstrInfo::hasNonExtEquivalent(const MachineInstr *MI) const {
3021 bool HexagonInstrInfo::hasPseudoInstrPair(const MachineInstr *MI) const {
3027 bool HexagonInstrInfo::hasUncondBranch(const MachineBasicBlock *B)
3040 bool HexagonInstrInfo::mayBeCurLoad(const MachineInstr *MI) const {
3049 bool HexagonInstrInfo::mayBeNewStore(const MachineInstr *MI) const {
3055 bool HexagonInstrInfo::producesStall(const MachineInstr *ProdMI,
3074 bool HexagonInstrInfo::producesStall(const MachineInstr *MI,
3101 bool HexagonInstrInfo::predCanBeUsedAsDotNew(const MachineInstr *MI,
3116 bool HexagonInstrInfo::PredOpcodeHasJMP_c(unsigned Opcode) const {
3126 bool HexagonInstrInfo::predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const {
3133 short HexagonInstrInfo::getAbsoluteForm(const MachineInstr *MI) const {
3138 unsigned HexagonInstrInfo::getAddrMode(const MachineInstr* MI) const {
3146 unsigned HexagonInstrInfo::getBaseAndOffset(const MachineInstr *MI,
3182 bool HexagonInstrInfo::getBaseAndOffsetPosition(const MachineInstr *MI,
3219 SmallVector<MachineInstr*, 2> HexagonInstrInfo::getBranchingInstrs(
3277 short HexagonInstrInfo::getBaseWithLongOffset(short Opcode) const {
3284 short HexagonInstrInfo::getBaseWithLongOffset(const MachineInstr *MI) const {
3289 short HexagonInstrInfo::getBaseWithRegOffset(const MachineInstr *MI) const {
3295 unsigned HexagonInstrInfo::getCExtOpNum(const MachineInstr *MI) const {
3302 HexagonII::CompoundGroup HexagonInstrInfo::getCompoundCandidateGroup(
3391 unsigned HexagonInstrInfo
3409 int HexagonInstrInfo::getCondOpcode(int Opc, bool invertPredicate) const {
3430 int HexagonInstrInfo::getDotCurOp(const MachineInstr* MI) const {
3529 int HexagonInstrInfo::getDotNewOp(const MachineInstr* MI) const {
3574 int HexagonInstrInfo::getDotNewPredJumpOp(const MachineInstr *MI,
3599 int HexagonInstrInfo::getDotNewPredOp(const MachineInstr *MI,
3618 int HexagonInstrInfo::getDotOldOp(const int opc) const {
3636 HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup(
3978 short HexagonInstrInfo::getEquivalentHWInstr(const MachineInstr *MI) const {
3984 MachineInstr *HexagonInstrInfo::getFirstNonDbgInst(MachineBasicBlock *BB)
3996 unsigned HexagonInstrInfo::getInstrTimingClassLatency(
4021 bool HexagonInstrInfo::getInvertedPredSense(
4031 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
4043 int HexagonInstrInfo::getMaxValue(const MachineInstr *MI) const {
4057 unsigned HexagonInstrInfo::getMemAccessSize(const MachineInstr* MI) const {
4064 int HexagonInstrInfo::getMinValue(const MachineInstr *MI) const {
4079 short HexagonInstrInfo::getNonExtOpcode(const MachineInstr *MI) const {
4104 bool HexagonInstrInfo::getPredReg(ArrayRef<MachineOperand> Cond,
4125 short HexagonInstrInfo::getPseudoInstrPair(const MachineInstr *MI) const {
4130 short HexagonInstrInfo::getRegForm(const MachineInstr *MI) const {
4139 unsigned HexagonInstrInfo::getSize(const MachineInstr *MI) const {
4174 uint64_t HexagonInstrInfo::getType(const MachineInstr* MI) const {
4180 unsigned HexagonInstrInfo::getUnits(const MachineInstr* MI) const {
4189 unsigned HexagonInstrInfo::getValidSubTargets(const unsigned Opcode) const {
4196 unsigned HexagonInstrInfo::nonDbgBBSize(const MachineBasicBlock *BB) const {
4201 unsigned HexagonInstrInfo::nonDbgBundleSize(
4212 void HexagonInstrInfo::immediateExtend(MachineInstr *MI) const {
4226 bool HexagonInstrInfo::invertAndChangeJumpTarget(
4247 void HexagonInstrInfo::genAllInsnTimingClasses(MachineFunction &MF) const {
4270 bool HexagonInstrInfo::reversePredSense(MachineInstr* MI) const {
4278 unsigned HexagonInstrInfo::reversePrediction(unsigned Opcode) const {
4290 bool HexagonInstrInfo::validateBranchCond(const ArrayRef<MachineOperand> &Cond)
4296 short HexagonInstrInfo::xformRegToImmOffset(const MachineInstr *MI) const {
