Lines Matching full:b000
616 defm loadrb : ld_idxd_shl<"memb", "LDrib", IntRegs, 0b000>;
713 def S4_storerb_ap : T_ST_absset <"memb", "STrib", IntRegs, 0b000, ByteAccess>;
742 let Inst{13-11} = 0b000;
788 def S4_storerb_ur : T_StoreAbsReg <"memb", "STrib", IntRegs, 0b000, ByteAccess>;
1020 defm storerb: ST_Idxd_shl<"memb", "STrib", IntRegs, 0b000>,
1624 defm J4_cmpeq : NVJrr_base<"cmp.eq", "CMPEQ", 0b000, 0>, PredRel;
1684 defm J4_cmpeqi : NVJri_base<"cmp.eq", "CMPEQ", 0b000>, PredRel;
1976 def S4_vxaddsubw : T_S3op_64 < "vxaddsubw", 0b01, 0b000, 0, 1>;
1982 def S4_vxaddsubhr : T_S3op_64 < "vxaddsubh", 0b11, 0b000, 0, 1, 1, 1>;
1987 def M4_mac_up_s1_sat: T_MType_acc_rr<"+= mpy", 0b011, 0b000, 0, [], 0, 1, 1>;
2011 let Inst{7-5} = 0b000;
2087 def A4_cround_ri : T_S2op_2_ii <"cround", 0b111, 0b000>;
2207 def M4_or_or : T_MType_acc_rr < "|= or", 0b110, 0b000, 0>;
2215 def M4_and_and : T_MType_acc_rr < "&= and", 0b010, 0b000, 0>;
2219 def M4_or_andn : T_MType_acc_rr < "|= and", 0b001, 0b000, 0, [], 1>;
2317 def S4_clbpnorm : T_COUNT_LEADING_64<"normamt", 0b011, 0b000>;
2343 let Inst{7-5} = 0b000;
2536 def M2_vmpy2su_s0 : T_XTYPE_mpy64 < "vmpyhsu", 0b000, 0b111, 1, 0, 0>;
3746 defm loadrb : LD_Abs<"memb", "LDrib", IntRegs, u16_0Imm, 0b000>;
3776 def L2_loadrbgp : T_LoadGP<"memb", "LDrib", IntRegs, u16_0Imm, 0b000>;
