Lines Matching refs:ResultReg
157 bool PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
443 unsigned ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
445 ResultReg).addFrameIndex(Addr.Base.FI).addImm(0);
446 Addr.Base.Reg = ResultReg;
462 bool PPCFastISel::PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
468 // If ResultReg is given, it determines the register class of the load.
476 (ResultReg ? MRI.getRegClass(ResultReg) :
524 bool IsVSSRC = (ResultReg != 0) && isVSSRCRegister(ResultReg);
525 bool IsVSFRC = (ResultReg != 0) && isVSFRCRegister(ResultReg);
534 if (ResultReg == 0)
535 ResultReg = createResultReg(UseRC);
550 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
558 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
582 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
612 unsigned ResultReg = 0;
613 if (!PPCEmitLoad(VT, ResultReg, Addr, RC))
615 updateValueMap(I, ResultReg);
989 unsigned ResultReg = 0;
990 if (!PPCEmitLoad(MVT::f64, ResultReg, Addr, RC, !IsSigned, LoadOpc))
993 return ResultReg;
1098 unsigned ResultReg = 0;
1099 if (!PPCEmitLoad(VT, ResultReg, Addr, RC, !IsSigned))
1102 return ResultReg;
1203 unsigned ResultReg = createResultReg(RC ? RC : &PPC::G8RCRegClass);
1252 ResultReg)
1255 updateValueMap(I, ResultReg);
1269 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
1271 updateValueMap(I, ResultReg);
1421 unsigned ResultReg = 0;
1425 ResultReg = createResultReg(CpyRC);
1428 TII.get(TargetOpcode::COPY), ResultReg)
1433 ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
1435 ResultReg).addReg(SourcePhysReg);
1442 ResultReg = createResultReg(&PPC::GPRCRegClass);
1446 TII.get(TargetOpcode::COPY), ResultReg)
1450 assert(ResultReg && "ResultReg unset!");
1452 CLI.ResultReg = ResultReg;
1800 unsigned ResultReg = createResultReg(&PPC::GPRCRegClass);
1803 ResultReg).addReg(SrcReg, 0, PPC::sub_32);
1804 SrcReg = ResultReg;
1841 unsigned ResultReg = createResultReg(RC);
1843 if (!PPCEmitIntExt(SrcVT, SrcReg, DestVT, ResultReg, IsZExt))
1846 updateValueMap(I, ResultReg);
2011 unsigned ResultReg = createResultReg(RC);
2016 TII.get(IsGPRC ? PPC::LI : PPC::LI8), ResultReg)
2025 TII.get(IsGPRC ? PPC::ORI : PPC::ORI8), ResultReg)
2030 TII.get(IsGPRC ? PPC::LIS : PPC::LIS8), ResultReg)
2033 return ResultReg;
2083 unsigned ResultReg = createResultReg(RC);
2085 ResultReg).addReg(TmpReg3).addImm(Lo);
2086 return ResultReg;
2166 unsigned ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
2168 ResultReg).addFrameIndex(SI->second).addImm(0);
2169 return ResultReg;
2179 // them. Thus ResultReg should be the def reg for the last redundant
2244 unsigned ResultReg = MI->getOperand(0).getReg();
2246 if (!PPCEmitLoad(VT, ResultReg, Addr, nullptr, IsZExt))
