Lines Matching full:pre_inc
97 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
98 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
99 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
100 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
101 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
102 setIndexedLoadAction(ISD::PRE_INC, MVT::f32, Legal);
103 setIndexedLoadAction(ISD::PRE_INC, MVT::f64, Legal);
104 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
105 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
106 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
107 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
108 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
109 setIndexedStoreAction(ISD::PRE_INC, MVT::f32, Legal);
110 setIndexedStoreAction(ISD::PRE_INC, MVT::f64, Legal);
723 setIndexedLoadAction(ISD::PRE_INC, MVT::v4f64, Legal);
724 setIndexedStoreAction(ISD::PRE_INC, MVT::v4f64, Legal);
769 setIndexedLoadAction(ISD::PRE_INC, MVT::v4f32, Legal);
770 setIndexedStoreAction(ISD::PRE_INC, MVT::v4f32, Legal);
2001 AM = ISD::PRE_INC;
2025 AM = ISD::PRE_INC;
2051 AM = ISD::PRE_INC;
6517 assert(LD->getAddressingMode() == ISD::PRE_INC &&
7988 assert(LN->getAddressingMode() == ISD::PRE_INC &&
8082 assert(SN->getAddressingMode() == ISD::PRE_INC &&
10724 assert(LD->getAddressingMode() == ISD::PRE_INC &&
