Lines Matching refs:Operands
94 // length for D(L,B)-style operands, otherwise it is null.
186 // Token operands
195 // Register operands.
207 // Access register operands. Access registers aren't exposed to LLVM
213 // Immediate operands.
225 // Immediate operands with optional TLS symbol.
230 // Memory operands.
254 assert(N == 3 && "Invalid number of operands");
269 assert(N == 1 && "Invalid number of operands");
273 assert(N == 1 && "Invalid number of operands");
278 assert(N == 1 && "Invalid number of operands");
282 assert(N == 2 && "Invalid number of operands");
288 assert(N == 3 && "Invalid number of operands");
295 assert(N == 3 && "Invalid number of operands");
302 assert(N == 2 && "Invalid number of operands");
370 OperandMatchResultTy parseRegister(OperandVector &Operands,
378 OperandMatchResultTy parseAddress(OperandVector &Operands,
382 OperandMatchResultTy parsePCRel(OperandVector &Operands, int64_t MinVal,
385 bool parseOperand(OperandVector &Operands, StringRef Mnemonic);
405 SMLoc NameLoc, OperandVector &Operands) override;
407 OperandVector &Operands, MCStreamer &Out,
412 OperandMatchResultTy parseGR32(OperandVector &Operands) {
413 return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, GR32Reg);
415 OperandMatchResultTy parseGRH32(OperandVector &Operands) {
416 return parseRegister(Operands, RegGR, SystemZMC::GRH32Regs, GRH32Reg);
418 OperandMatchResultTy parseGRX32(OperandVector &Operands) {
421 OperandMatchResultTy parseGR64(OperandVector &Operands) {
422 return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, GR64Reg);
424 OperandMatchResultTy parseGR128(OperandVector &Operands) {
425 return parseRegister(Operands, RegGR, SystemZMC::GR128Regs, GR128Reg);
427 OperandMatchResultTy parseADDR32(OperandVector &Operands) {
428 return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, ADDR32Reg);
430 OperandMatchResultTy parseADDR64(OperandVector &Operands) {
431 return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, ADDR64Reg);
433 OperandMatchResultTy parseADDR128(OperandVector &Operands) {
436 OperandMatchResultTy parseFP32(OperandVector &Operands) {
437 return parseRegister(Operands, RegFP, SystemZMC::FP32Regs, FP32Reg);
439 OperandMatchResultTy parseFP64(OperandVector &Operands) {
440 return parseRegister(Operands, RegFP, SystemZMC::FP64Regs, FP64Reg);
442 OperandMatchResultTy parseFP128(OperandVector &Operands) {
443 return parseRegister(Operands, RegFP, SystemZMC::FP128Regs, FP128Reg);
445 OperandMatchResultTy parseVR32(OperandVector &Operands) {
446 return parseRegister(Operands, RegV, SystemZMC::VR32Regs, VR32Reg);
448 OperandMatchResultTy parseVR64(OperandVector &Operands) {
449 return parseRegister(Operands, RegV, SystemZMC::VR64Regs, VR64Reg);
451 OperandMatchResultTy parseVF128(OperandVector &Operands) {
454 OperandMatchResultTy parseVR128(OperandVector &Operands) {
455 return parseRegister(Operands, RegV, SystemZMC::VR128Regs, VR128Reg);
457 OperandMatchResultTy parseBDAddr32(OperandVector &Operands) {
458 Operands, BDMem, SystemZMC::GR32Regs, ADDR32Reg);
460 OperandMatchResultTy parseBDAddr64(OperandVector &Operands) {
461 return parseAddress(Operands, BDMem, SystemZMC::GR64Regs, ADDR64Reg);
463 OperandMatchResultTy parseBDXAddr64(OperandVector &Operands) {
464 return parseAddress(Operands, BDXMem, SystemZMC::GR64Regs, ADDR64Reg);
466 OperandMatchResultTy parseBDLAddr64(OperandVector &Operands) {
467 return parseAddress(Operands, BDLMem, SystemZMC::GR64Regs, ADDR64Reg);
469 OperandMatchResultTy parseBDVAddr64(OperandVector &Operands) {
470 return parseAddress(Operands, BDVMem, SystemZMC::GR64Regs, ADDR64Reg);
472 OperandMatchResultTy parseAccessReg(OperandVector &Operands);
473 OperandMatchResultTy parsePCRel16(OperandVector &Operands) {
474 return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, false);
476 OperandMatchResultTy parsePCRel32(OperandVector &Operands) {
477 return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, false);
479 OperandMatchResultTy parsePCRelTLS16(OperandVector &Operands) {
480 return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, true);
482 OperandMatchResultTy parsePCRelTLS32(OperandVector &Operands) {
483 return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, true);
558 // Parse a register and add it to Operands. The other arguments are as above.
560 SystemZAsmParser::parseRegister(OperandVector &Operands, RegisterGroup Group,
570 Operands.push_back(SystemZOperand::createReg(Kind, Reg.Num,
637 // Parse a memory operand and add it to Operands. The other arguments
640 SystemZAsmParser::parseAddress(OperandVector &Operands, MemoryKind MemKind,
677 Operands.push_back(SystemZOperand::createMem(MemKind, RegKind, Base, Disp,
708 OperandVector &Operands) {
709 Operands.push_back(SystemZOperand::createToken(Name, NameLoc));
711 // Read the remaining operands.
714 if (parseOperand(Operands, Name)) {
719 // Read any subsequent operands.
722 if (parseOperand(Operands, Name)) {
739 bool SystemZAsmParser::parseOperand(OperandVector &Operands,
743 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
753 // Check for a register. All real register operands should have used
761 Operands.push_back(SystemZOperand::createInvalid(Reg.StartLoc, Reg.EndLoc));
766 // real address operands should have used a context-dependent parse routine,
779 Operands.push_back(SystemZOperand::createInvalid(StartLoc, EndLoc));
781 Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
786 OperandVector &Operands,
793 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
820 if (ErrorInfo >= Operands.size())
821 return Error(IDLoc, "too few operands for instruction");
823 ErrorLoc = ((SystemZOperand &)*Operands[ErrorInfo]).getStartLoc();
838 SystemZAsmParser::parseAccessReg(OperandVector &Operands) {
846 Operands.push_back(SystemZOperand::createAccessReg(Reg.Num,
853 SystemZAsmParser::parsePCRel(OperandVector &Operands, int64_t MinVal,
920 Operands.push_back(SystemZOperand::createImmTLS(Expr, Sym,
923 Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
