Lines Matching refs:SegReg
700 ParseIntelSegmentOverride(unsigned SegReg, SMLoc Start, unsigned Size);
705 std::unique_ptr<X86Operand> ParseIntelBracExpression(unsigned SegReg,
713 std::unique_ptr<X86Operand> ParseMemOperand(unsigned SegReg, SMLoc StartLoc);
716 CreateMemForInlineAsm(unsigned SegReg, const MCExpr *Disp, unsigned BaseReg,
998 return X86Operand::CreateMem(getPointerWidth(), /*SegReg=*/0, Disp,
1007 return X86Operand::CreateMem(getPointerWidth(), /*SegReg=*/0, Disp,
1112 FinalOp.Mem.SegReg = OrigOp.Mem.SegReg;
1160 unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg,
1198 return X86Operand::CreateMem(getPointerWidth(), SegReg, Disp, BaseReg,
1388 X86AsmParser::ParseIntelBracExpression(unsigned SegReg, SMLoc Start,
1445 if (!SegReg)
1447 return X86Operand::CreateMem(getPointerWidth(), SegReg, Disp, 0, 0, 1,
1455 return X86Operand::CreateMem(getPointerWidth(), SegReg, Disp, BaseReg,
1460 return CreateMemForInlineAsm(SegReg, Disp, BaseReg, IndexReg, Scale, Start,
1515 X86AsmParser::ParseIntelSegmentOverride(unsigned SegReg, SMLoc Start,
1518 assert(SegReg != 0 && "Tried to parse a segment override without a segment!");
1537 return X86Operand::CreateMem(getPointerWidth(), SegReg, Disp,
1544 return ParseIntelBracExpression(SegReg, Start, ImmDisp, Size);
1560 return CreateMemForInlineAsm(/*SegReg=*/0, Val, /*BaseReg=*/0,/*IndexReg=*/0,
1611 return ParseIntelBracExpression(/*SegReg=*/0, Start, ImmDisp, Size);
1629 return CreateMemForInlineAsm(/*SegReg=*/0, Val, /*BaseReg=*/0, /*IndexReg=*/0,
1657 return X86Operand::CreateMem(getPointerWidth(), /*SegReg=*/0, Disp,
1871 return ParseIntelSegmentOverride(/*SegReg=*/RegNo, Start, Size);
1995 std::unique_ptr<X86Operand> X86AsmParser::ParseMemOperand(unsigned SegReg,
2012 if (SegReg == 0)
2014 return X86Operand::CreateMem(getPointerWidth(), SegReg, Disp, 0, 0, 1,
2040 if (SegReg == 0)
2043 return X86Operand::CreateMem(getPointerWidth(), SegReg, Disp, 0, 0, 1,
2160 if (SegReg || BaseReg || IndexReg)
2161 return X86Operand::CreateMem(getPointerWidth(), SegReg, Disp, BaseReg,
2377 if (Op.isMem() && Op.Mem.SegReg == 0 &&
2390 if (Op.isMem() && Op.Mem.SegReg == 0 &&
