Lines Matching full:srcreg
1210 unsigned SrcReg = Reg + VA.getValNo();
1226 SrcReg = fastEmitZExtFromI1(MVT::i8, SrcReg, /*TODO: Kill=*/false);
1231 SrcReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Op,
1232 SrcReg, /*TODO: Kill=*/false);
1237 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
1242 TII.get(TargetOpcode::COPY), DstReg).addReg(SrcReg);
2539 unsigned SrcReg = createResultReg(RC);
2541 TII.get(TargetOpcode::COPY), SrcReg).addReg(FrameReg);
2553 TII.get(Opc), DestReg), SrcReg);
2554 SrcReg = DestReg;
2557 updateValueMap(II, SrcReg);
2667 unsigned SrcReg = getRegForValue(SrcVal);
2669 if (SrcReg == 0)
2687 MIB.addReg(SrcReg);
2966 unsigned SrcReg;
2969 case MVT::i32: SrcReg = GPR32ArgRegs[GPRIdx++]; break;
2970 case MVT::i64: SrcReg = GPR64ArgRegs[GPRIdx++]; break;
2972 case MVT::f64: SrcReg = XMMArgRegs[FPRIdx++]; break;
2974 unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, RC);
3485 unsigned SrcReg = fastEmitInst_(X86::MOV32r0, &X86::GR32RegClass);
3490 return fastEmitInst_extractsubreg(MVT::i8, SrcReg, /*Kill=*/true,
3493 return fastEmitInst_extractsubreg(MVT::i16, SrcReg, /*Kill=*/true,
3496 return SrcReg;
3501 .addImm(0).addReg(SrcReg).addImm(X86::sub_32bit);
3525 unsigned SrcReg = fastEmitInst_i(Opc, &X86::GR32RegClass, Imm);
3529 .addImm(0).addReg(SrcReg).addImm(X86::sub_32bit);
