Lines Matching refs:IndexReg
253 /// IndexReg field of the addressing mode will be updated to match in this case.
258 AM.IndexReg = constrainOperandRegClass(MIB->getDesc(), AM.IndexReg,
722 (AM.Base.Reg == 0 && AM.IndexReg == 0)) {
741 assert(AM.Base.Reg == 0 && AM.IndexReg == 0);
803 if (AM.IndexReg == 0) {
805 AM.IndexReg = getRegForValue(V);
806 return AM.IndexReg != 0;
890 unsigned IndexReg = AM.IndexReg;
922 if (IndexReg == 0 &&
927 IndexReg = getRegForGEPIndex(Op).first;
928 if (IndexReg == 0)
941 AM.IndexReg = IndexReg;
1044 (AM.Base.Reg != 0 || AM.IndexReg != 0))
1064 assert(AM.Base.Reg == 0 && AM.IndexReg == 0);
1079 if (AM.IndexReg == 0) {
1081 AM.IndexReg = getRegForValue(V);
1082 return AM.IndexReg != 0;
3625 AM.IndexReg == 0 && AM.Disp == 0 && AM.GV == nullptr)
3765 if (!MO.isReg() || MO.isDef() || MO.getReg() != AM.IndexReg)
3768 unsigned IndexReg = constrainOperandRegClass(Result->getDesc(),
3770 if (IndexReg == MO.getReg())
3772 MO.setReg(IndexReg);
