Lines Matching full:vr128
43 def r : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
44 (ins VR128:$src1, VR128:$src2, VR128:$src3),
47 [(set VR128:$dst, (OpVT128 (Op VR128:$src2,
48 VR128:$src1, VR128:$src3)))]>;
51 def m : FMA3<opc, MRMSrcMem, (outs VR128:$dst),
52 (ins VR128:$src1, VR128:$src2, f128mem:$src3),
55 [(set VR128:$dst, (OpVT128 (Op VR128:$src2, VR128:$src1,
229 fma3s_int_forms<opc132, opc213, opc231, OpStr, "ss", VR128, ssmem>;
234 fma3s_int_forms<opc132, opc213, opc231, OpStr, "sd", VR128, sdmem>,
242 def : Pat<(IntF32 VR128:$src1, VR128:$src2, VR128:$src3),
244 $src1, $src2, $src3), VR128)>;
246 def : Pat<(IntF64 VR128:$src1, VR128:$src2, VR128:$src3),
248 $src1, $src2, $src3), VR128)>;
302 def rr_Int : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
303 (ins VR128:$src1, VR128:$src2, VR128:$src3),
306 [(set VR128:$dst,
307 (Int VR128:$src1, VR128:$src2, VR128:$src3))]>, VEX_W, VEX_LIG, MemOp4;
308 def rm_Int : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
309 (ins VR128:$src1, VR128:$src2, memop:$src3),
312 [(set VR128:$dst, (Int VR128:$src1, VR128:$src2,
314 def mr_Int : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
315 (ins VR128:$src1, memop:$src2, VR128:$src3),
318 [(set VR128:$dst,
319 (Int VR128:$src1, mem_cpat:$src2, VR128:$src3))]>, VEX_LIG;
327 def rr : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
328 (ins VR128:$src1, VR128VR128:$src3),
331 [(set VR128:$dst,
332 (OpVT128 (OpNode VR128:$src1, VR128:$src2, VR128:$src3)))]>,
334 def rm : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
335 (ins VR128:$src1, VR128:$src2, f128mem:$src3),
338 [(set VR128:$dst, (OpNode VR128:$src1, VR128:$src2,
340 def mr : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
341 (ins VR128:$src1, f128mem:$src2, VR128:$src3),
344 [(set VR128:$dst,
345 (OpNode VR128:$src1, (ld_frag128 addr:$src2), VR128:$src3))]>;
368 def rr_REV : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
369 (ins VR128:$src1, VR128:$src2, VR128:$src3),
