Cross Reference: /external/llvm/test/TableGen/TargetInstrSpec.td

Lines Matching full:vr128

4 // CHECK: [(set VR128:$dst, (int_x86_sse2_add_pd VR128:$src1, VR128:$src2))]
5 // CHECK-NOT: [(set VR128:$dst, (int_x86_sse2_add_pd VR128:$src1, VR128:$src2))]
7 // CHECK: [(set VR128:$dst, (int_x86_sse2_add_ps VR128:$src1, VR128:$src2))]
8 // CHECK-NOT: [(set VR128:$dst, (int_x86_sse2_add_ps VR128:$src1, VR128:$src2))]
64 def VR128 : RegisterClass<[v2i64, v2f64],
86   def PS : Inst<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
91 				          !subst(REGCLASS, VR128, Decls.operand))))>;
93   def PD : Inst<opcode, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
98 				          !subst(REGCLASS, VR128, Decls.operand))))>;

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