Lines Matching defs:fmask
337 /* Initialize the sampler view for FMASK. */
338 if (image->fmask.size) {
343 va = gpu_address + image->offset + image->fmask.offset;
370 S_008F1C_TILING_INDEX(image->fmask.tile_mode_index) |
373 S_008F20_PITCH(image->fmask.pitch_in_pixels - 1);
461 /* FMASK is allocated like an ordinary texture. */
462 struct radeon_surf fmask = image->surface;
466 fmask.bo_alignment = 0;
467 fmask.bo_size = 0;
468 fmask.nsamples = 1;
469 fmask.flags |= RADEON_SURF_FMASK;
472 * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
473 * destination buffer must have an FMASK too. */
474 fmask.flags = RADEON_SURF_CLR(fmask.flags, MODE);
475 fmask.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
477 fmask.flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
482 fmask.bpe = 1;
485 fmask.bpe = 4;
491 device->ws->surface_init(device->ws, &fmask);
492 assert(fmask.level[0].mode == RADEON_SURF_MODE_2D);
494 out->slice_tile_max = (fmask.level[0].nblk_x * fmask.level[0].nblk_y) / 64;
498 out->tile_mode_index = fmask.tiling_index[0];
499 out->pitch_in_pixels = fmask.level[0].nblk_x;
500 out->bank_height = fmask.bankh;
501 out->alignment = MAX2(256, fmask.bo_alignment);
502 out->size = fmask.bo_size;
509 radv_image_get_fmask_info(device, image, image->samples, &image->fmask);
511 image->fmask.offset = align64(image->size, image->fmask.alignment);
512 image->size = image->fmask.offset + image->fmask.size;
513 image->alignment = MAX2(image->alignment, image->fmask.alignment);
