Lines Matching refs:dw1
90 uint32_t dw0, dw1, dw2;
99 dw1 = 0;
140 dw1 |= front_p->test_mask << GEN6_ZS_DW1_STENCIL_TEST_MASK__SHIFT |
160 cc->ds[1] = dw1;
174 uint32_t dw1, dw2;
182 dw1 = 0;
191 dw1 |= GEN8_ZS_DW1_STENCIL_TEST_ENABLE;
194 dw1 |= GEN8_ZS_DW1_STENCIL1_ENABLE;
203 dw1 |= front->fail_op << GEN8_ZS_DW1_STENCIL_FAIL_OP__SHIFT |
213 dw1 |= GEN8_ZS_DW1_STENCIL_WRITE_ENABLE;
222 dw1 |= GEN8_ZS_DW1_DEPTH_TEST_ENABLE |
225 dw1 |= GEN6_COMPAREFUNCTION_ALWAYS << GEN8_ZS_DW1_DEPTH_FUNC__SHIFT;
229 dw1 |= GEN8_ZS_DW1_DEPTH_WRITE_ENABLE;
232 cc->ds[0] = dw1;
490 uint32_t dw0, dw1;
505 dw1 = GEN6_RT_DW1_COLORCLAMP_RTFORMAT |
510 dw1 |= GEN6_RT_DW1_ALPHA_TO_COVERAGE;
519 dw1 |= GEN6_RT_DW1_ALPHA_TO_COVERAGE_DITHER;
523 dw1 |= GEN6_RT_DW1_ALPHA_TO_ONE;
526 dw1 |= GEN6_RT_DW1_ALPHA_TEST_ENABLE |
535 dw1 |= GEN6_COMPAREFUNCTION_ALWAYS <<
540 dw1 |= GEN6_RT_DW1_DITHER_ENABLE;
542 dw1_invariant = dw1;
566 dw1 = dw1_invariant |
570 dw1 |= GEN6_RT_DW1_LOGICOP_ENABLE |
575 dw_rt[2 * i + 1] = dw1;
593 uint32_t dw_rt[2 * ILO_STATE_CC_BLEND_MAX_RT_COUNT], dw0, dw1;
626 dw1 = GEN8_RT_DW1_COLORCLAMP_RTFORMAT |
631 dw1 |= GEN8_RT_DW1_LOGICOP_ENABLE |
636 dw_rt[2 * i + 1] = dw1;
678 uint32_t dw1;
682 dw1 = 0;
685 dw1 |= GEN8_PS_BLEND_DW1_ALPHA_TO_COVERAGE;
688 dw1 |= GEN8_PS_BLEND_DW1_ALPHA_TEST_ENABLE;
697 dw1 |= rt0.a_src << GEN8_PS_BLEND_DW1_RT0_SRC_ALPHA_FACTOR__SHIFT |
704 dw1 |= GEN8_PS_BLEND_DW1_WRITABLE_RT;
710 dw1 |= GEN8_PS_BLEND_DW1_RT0_BLEND_ENABLE;
713 dw1 |= GEN8_PS_BLEND_DW1_RT0_INDEPENDENT_ALPHA_ENABLE;
718 cc->blend[0] = dw1;
786 uint32_t dw1 = cc->ds[0];
789 if (dw1 & GEN8_ZS_DW1_STENCIL_TEST_ENABLE) {
790 const bool twosided_enable = (dw1 & GEN8_ZS_DW1_STENCIL1_ENABLE);
798 dw1 |= GEN8_ZS_DW1_STENCIL_WRITE_ENABLE;
800 dw1 &= ~GEN8_ZS_DW1_STENCIL_WRITE_ENABLE;
809 cc->ds[0] = dw1;
813 uint32_t dw1 = cc->ds[1];
828 dw1 =
836 cc->ds[1] = dw1;
