Lines Matching refs:dw1
45 gen6_wa_pre_pipe_control(struct ilo_render *r, uint32_t dw1)
63 const bool direct_wa_cond = (dw1 & GEN6_PIPE_CONTROL_WRITE__MASK) &&
64 !(dw1 & GEN6_PIPE_CONTROL_RENDER_CACHE_FLUSH);
65 const bool indirect_wa_cond = (dw1 & GEN6_PIPE_CONTROL_DEPTH_STALL) |
66 (dw1 & GEN6_PIPE_CONTROL_RENDER_CACHE_FLUSH);
79 * - Depth Cache Flush Enable ([0] of DW1)
80 * - Stall at Pixel Scoreboard ([1] of DW1)
81 * - Depth Stall ([13] of DW1)
82 * - Post-Sync Operation ([13] of DW1)
83 * - Render Target Cache Flush Enable ([12] of DW1)
84 * - Notify Enable ([8] of DW1)"
126 const uint32_t dw1 = GEN6_PIPE_CONTROL_CS_STALL;
128 if ((r->state.current_pipe_control_dw1 & dw1) != dw1)
129 gen6_wa_pre_pipe_control(r, dw1);
130 if ((r->state.current_pipe_control_dw1 & dw1) != dw1)
131 ilo_render_pipe_control(r, dw1);
142 const uint32_t dw1 = GEN6_PIPE_CONTROL_DEPTH_STALL |
146 if ((r->state.current_pipe_control_dw1 & dw1) != dw1)
147 gen6_wa_pre_pipe_control(r, dw1);
148 if ((r->state.current_pipe_control_dw1 & dw1) != dw1)
149 ilo_render_pipe_control(r, dw1);
166 const uint32_t dw1 = GEN6_PIPE_CONTROL_WRITE_IMM |
169 if ((r->state.current_pipe_control_dw1 & dw1) != dw1)
170 gen6_wa_pre_pipe_control(r, dw1);
171 if ((r->state.current_pipe_control_dw1 & dw1) != dw1)
172 ilo_render_pipe_control(r, dw1);
182 * field set (DW1 Bit 1), must be issued prior to any change to the
185 const uint32_t dw1 = GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL;
189 if ((r->state.current_pipe_control_dw1 & dw1) != dw1)
190 gen6_wa_pre_pipe_control(r, dw1);
191 if ((r->state.current_pipe_control_dw1 & dw1) != dw1)
192 ilo_render_pipe_control(r, dw1);
206 const uint32_t dw1 = GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH |
211 if ((r->state.current_pipe_control_dw1 & dw1) != dw1)
212 gen6_wa_pre_pipe_control(r, dw1);
213 if ((r->state.current_pipe_control_dw1 & dw1) != dw1)
214 ilo_render_pipe_control(r, dw1);
