Lines Matching refs:tiling
220 winsys_to_surface_tiling(enum intel_tiling_mode tiling)
222 switch (tiling) {
230 assert(!"unknown tiling");
236 surface_to_winsys_tiling(enum gen_surface_tiling tiling)
238 switch (tiling) {
246 assert(!"unknown tiling");
300 /* set the tiling for transfer and export */
301 if (bo && (tex->image.tiling == GEN6_TILING_X ||
302 tex->image.tiling == GEN6_TILING_Y)) {
303 const enum intel_tiling_mode tiling =
304 surface_to_winsys_tiling(tex->image.tiling);
306 if (intel_bo_set_tiling(bo, tiling, tex->image.bo_stride)) {
442 enum intel_tiling_mode tiling;
447 tex->image.bo_height, &tiling, &pitch);
450 const uint8_t valid_tilings = 1 << winsys_to_surface_tiling(tiling);
533 /* require on-the-fly tiling/untiling or format conversion */
534 if (img->tiling == GEN8_TILING_W || *separate_stencil ||
579 enum intel_tiling_mode tiling;
583 if (tex->image.tiling == GEN8_TILING_W)
584 tiling = INTEL_TILING_NONE;
586 tiling = surface_to_winsys_tiling(tex->image.tiling);
588 err = intel_winsys_export_handle(is->dev.winsys, tex->vma.bo, tiling,
