Lines Matching refs:hw
92 uint32_t *hw = &fp->insn[fpc->inst_offset];
98 hw[0] |= (src.reg.index << NVFX_FP_OP_INPUT_SRC_SHIFT);
110 hw = &fp->insn[fpc->inst_offset];
123 hw = &fp->insn[fpc->inst_offset];
151 hw[1] |= (1 << (29 + pos));
158 hw[pos + 1] |= sr;
165 uint32_t *hw = &fp->insn[fpc->inst_offset];
172 hw[0] |= NVFX_FP_OP_OUT_REG_HALF;
181 hw[0] |= (1 << 30);
187 hw[0] |= (dst.index << NVFX_FP_OP_OUT_REG_SHIFT);
194 uint32_t *hw;
199 hw = &fp->insn[fpc->inst_offset];
200 memset(hw, 0, sizeof(uint32_t) * 4);
204 hw[0] |= (insn.op << NVFX_FP_OP_OPCODE_SHIFT);
205 hw[0] |= (insn.mask << NVFX_FP_OP_OUTMASK_SHIFT);
206 hw[2] |= (insn.scale << NVFX_FP_OP_DST_SCALE_SHIFT);
209 hw[0] |= NVFX_FP_OP_OUT_SAT;
212 hw[0] |= NVFX_FP_OP_COND_WRITE_ENABLE;
213 hw[1] |= (insn.cc_test << NVFX_FP_OP_COND_SHIFT);
214 hw[1] |= ((insn.cc_swz[0] << NVFX_FP_OP_COND_SWZ_X_SHIFT) |
221 hw[0] |= (insn.unit << NVFX_FP_OP_TEX_UNIT_SHIFT);
244 uint32_t *hw;
250 hw = &fpc->fp->insn[fpc->inst_offset];
252 hw[0] = (NV40_FP_OP_BRA_OPCODE_IF << NVFX_FP_OP_OPCODE_SHIFT) |
256 hw[1] = (0 << NVFX_FP_OP_COND_SWZ_X_SHIFT) |
261 hw[2] = 0; /* | NV40_FP_OP_OPCODE_IS_BRANCH | else_offset */
262 hw[3] = 0; /* | endif_offset */
271 uint32_t *hw;
274 hw = &fpc->fp->insn[fpc->inst_offset];
276 hw[0] = (NV40_FP_OP_BRA_OPCODE_CAL << NVFX_FP_OP_OPCODE_SHIFT);
278 hw[1] = (NVFX_SWZ_IDENTITY << NVFX_FP_OP_COND_SWZ_ALL_SHIFT) |
280 hw[2] = NV40_FP_OP_OPCODE_IS_BRANCH; /* | call_offset */
281 hw[3] = 0;
290 uint32_t *hw;
293 hw = &fpc->fp->insn[fpc->inst_offset];
295 hw[0] = (NV40_FP_OP_BRA_OPCODE_RET << NVFX_FP_OP_OPCODE_SHIFT);
297 hw[1] = (NVFX_SWZ_IDENTITY << NVFX_FP_OP_COND_SWZ_ALL_SHIFT) |
299 hw[2] = NV40_FP_OP_OPCODE_IS_BRANCH; /* | call_offset */
300 hw[3] = 0;
307 uint32_t *hw;
310 hw = &fpc->fp->insn[fpc->inst_offset];
312 hw[0] = (NV40_FP_OP_BRA_OPCODE_REP << NVFX_FP_OP_OPCODE_SHIFT) |
316 hw[1] = (NVFX_SWZ_IDENTITY << NVFX_FP_OP_COND_SWZ_ALL_SHIFT) |
318 hw[2] = NV40_FP_OP_OPCODE_IS_BRANCH |
322 hw[3] = 0; /* | end_offset */
336 uint32_t *hw;
339 hw = &fpc->fp->insn[fpc->inst_offset];
341 hw[0] = (NV40_FP_OP_BRA_OPCODE_IF << NVFX_FP_OP_OPCODE_SHIFT) |
345 hw[1] = (NVFX_SWZ_IDENTITY << NVFX_FP_OP_COND_SWZ_X_SHIFT) |
347 hw[2] = NV40_FP_OP_OPCODE_IS_BRANCH; /* | else_offset */
348 hw[3] = 0; /* | endif_offset */
361 uint32_t *hw;
364 hw = &fpc->fp->insn[fpc->inst_offset];
366 hw[0] = (NV40_FP_OP_BRA_OPCODE_BRK << NVFX_FP_OP_OPCODE_SHIFT) |
369 hw[1] = (NVFX_SWZ_IDENTITY << NVFX_FP_OP_COND_SWZ_X_SHIFT) |
371 hw[2] = NV40_FP_OP_OPCODE_IS_BRANCH;
372 hw[3] = 0;
797 uint32_t *hw;
801 hw = &fpc->fp->insn[util_dynarray_top(&fpc->if_stack, unsigned)];
802 hw[2] = NV40_FP_OP_OPCODE_IS_BRANCH | fpc->fp->insn_len;
808 uint32_t *hw;
812 hw = &fpc->fp->insn[util_dynarray_pop(&fpc->if_stack, unsigned)];
813 if(!hw[2])
814 hw[2] = NV40_FP_OP_OPCODE_IS_BRANCH | fpc->fp->insn_len;
815 hw[3] = fpc->fp->insn_len;
888 unsigned hw;
892 hw = NVFX_FP_OP_INPUT_SRC_POSITION;
895 hw = NVFX_FP_OP_INPUT_SRC_COL0 + fdec->Semantic.Index;
898 hw = NVFX_FP_OP_INPUT_SRC_FOGC;
901 hw = NV40_FP_OP_INPUT_SRC_FACING;
908 hw = NVFX_FP_OP_INPUT_SRC_TC(fdec->Semantic.Index);
919 fpc->r_input[idx] = nvfx_reg(NVFXSR_INPUT, hw);
929 unsigned hw;
934 for (hw = 0; hw < num_texcoords; hw++) {
935 if (fpc->fp->texcoord[hw] == 0xffff) {
936 if (hw <= 7) {
937 fpc->fp->texcoords |= (0x1 << hw);
938 fpc->fp->vp_or |= (0x00004000 << hw);
940 fpc->fp->vp_or |= (0x00001000 << (hw - 8));
943 fpc->fp->texcoord[hw] = 0xfffe;
944 fpc->fp->point_sprite_control |= (0x00000100 << hw);
946 fpc->fp->texcoord[hw] = fdec->Semantic.Index + 8;
948 hw = NVFX_FP_OP_INPUT_SRC_TC(hw);
949 fpc->r_input[idx] = nvfx_reg(NVFXSR_INPUT, hw);
964 unsigned hw;
968 hw = 1;
971 hw = ~0;
973 case 0: hw = 0; break;
974 case 1: hw = 2; break;
975 case 2: hw = 3; break;
976 case 3: hw = 4; break;
978 if(hw > ((fpc->is_nv4x) ? 4 : 2)) {
988 fpc->r_result[idx] = nvfx_reg(NVFXSR_OUTPUT, hw);
989 fpc->r_temps |= (1ULL << hw);
