Lines Matching defs:in
6 * to deal in the Software without restriction, including without limitation
12 * paragraph) shall be included in all copies or substantial portions of the
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
45 -These 8xx t-slot only ops are implemented in all vector slots.
51 These 8xx t-slot only opcodes become vector ops in the z, y, and
58 result is required to be in the w slot, the opcode above may be
59 issued in the w slot as well.
187 /* only disable for vertex shaders in tess paths */
232 /* Store the shader in a buffer. */
334 /* evergreen/cayman also store sample mask in face register */
336 /* sample id is .w component stored in fixed point position register */
548 * Special export handling in shaders
555 * The use of the values exported in 61-63 are controlled by PA_CL_VS_OUT_CNTL:
556 * VS_OUT_MISC_VEC_ENA - enables the use of all fields in export 61
557 * USE_VTX_POINT_SIZE - point size in the X channel of export 61
558 * USE_VTX_EDGE_FLAG - edge flag in the Y channel of export 61
559 * USE_VTX_RENDER_TARGET_INDX - render target index in
560 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
561 * USE_VTX_KILL_FLAG - kill flag in the Z channel of export 61 (mutually
570 * The use of the values exported in the computed Z vector are controlled
572 * Z_EXPORT_ENABLE - Z as a float in RED
573 * STENCIL_REF_EXPORT_ENABLE - stencil ref as int in GREEN
574 * COVERAGE_TO_MASK_ENABLE - alpha to mask in ALPHA
575 * MASK_EXPORT_ENABLE - pixel sample mask in BLUE
628 /* same explanation as in the default statement,
792 /* put it in temp_reg.x */
894 /* FIXME probably skip inputs if they aren't passed in the ring */
1082 { false, &ctx->face_gpr, TGSI_SEMANTIC_SAMPLEMASK, ~0u }, /* lives in Front Face GPR.z */
1084 { false, &ctx->fixed_pt_position_gpr, TGSI_SEMANTIC_SAMPLEID, TGSI_SEMANTIC_SAMPLEPOS } /* SAMPLEID is in Fixed Point Position GPR.w */
1249 vtx.src_gpr = ctx->fixed_pt_position_gpr; // SAMPLEID is in .w;
1473 /* offsets of per-vertex data in ESGS ring are passed to GS in R0.x, R0.y,
1590 /* primitive id is in R0.z */
1627 /* this will return with the dw address in temp_reg.x */
1652 * in a primitive), calculate the base address of the vertex. */
1717 /* add to base_addr - passed in temp_reg.x */
1789 /* the base address is now in temp.x */
1815 /* the base address is now in temp.x */
1836 /* the base address is now in temp.x */
2478 struct r600_shader_io *in = &ctx->gs_for_vs->input[k];
2480 if (in->name == out->name && in->sid == out->sid)
2481 ring_offset = in->ring_offset;
2522 output.array_base = ring_offset >> 2; /* in dwords */
2526 output.array_base = ring_offset >> 2; /* in dwords */
2624 0, 1); /* rel id in r0.y? */
2687 /* the base address is now in temp.x */
2831 /* TF_WRITE takes index in R.x, value in R.y */
3016 * Other special values are shown in the list below.
3045 /* FIXME 1 would be enough in some cases (3 or less input vertices) */
3198 // Non LLVM path computes it later (in process_twoside_color)
4405 * in DMUL lowering. */
4749 /* kill must be last in ALU */
5118 * and fixing the sign of the result in the end.
7039 /* have to multiply original layer by 8 and add to face id (temp.w) in Z */
7440 encoded in the instruction are ignored. */
7594 /* Put the depth for comparison in W.
7595 * TGSI_TEXTURE_SHADOW2D_ARRAY already has the depth in W.
7596 * Some instructions expect the depth in Z. */
8560 * NOTE: it seems we also need to reserve additional element in some
8561 * other cases, e.g. when we have 4 levels of PUSH_VPM in the shader,
8574 * for all chips, so we use 4 in the final formula, not the real entry_size
8747 R600_ERR("if/endif unbalanced in shader\n");
8783 R600_ERR("loop/endloop in shader code are not paired.\n");
